中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

324 records (took 0.023 seconds)

    MULTIFUNCTIONAL AND MULTI-BIT RESISTIVE STORAGE MEMORIES
    1.
    发明申请
    MULTIFUNCTIONAL AND MULTI-BIT RESISTIVE STORAGE MEMORIES 审中-公开
    多功能和多位电阻存储器

    公开(公告)号：WO2018006131A1

    公开(公告)日：2018-01-11

    申请号：PCT/AU2017/050699

    申请日：2017-07-06

    Applicant: RMIT UNIVERSITY

    Inventor： SRIRAM, Sharath ,  AHMED, Taimur ,  WALIA, Sumeet ,  BHASKARAN, Madhu

    IPC: H01L45/00 ,  H01L27/24 ,  G11C11/56

    CPC classification number: G11C13/0069 ,  G11C11/5685 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

    Abstract: A memristor device is provided, comprising a first electrode; a second electrode; a cathode metal layer disposed on a surface of the first electrode; and an active region disposed between and in electrical contact with the second electrode and the cathode metal layer, the active region comprising at least one layer of an amorphous metal oxide, wherein the amorphous metal oxide comprises doping atoms of a dopant element selected from the group consisting of aluminium, nickel, iron and chromium, and wherein when a switching voltage is applied between the first and second electrodes, the active region exhibits a resistive switching behaviour. Also provided is a method of fabricating such a memristor device.

    Abstract translation: 提供了一种忆阻器装置，其包括第一电极; 第二电极; 设置在所述第一电极的表面上的阴极金属层; 以及设置在第二电极和阴极金属层之间并与第二电极和阴极金属层电接触的有源区，有源区包括至少一层非晶金属氧化物， 由铝，镍，铁和铬组成，并且其中当在第一和第二电极之间施加开关电压时，有源区呈现出电阻切换行为。 还提供了制造这种忆阻器器件的方法。

    DIRECT FORMATION POROUS MATERIALS FOR ELECTRONIC DEVICES
    2.
    发明申请
    DIRECT FORMATION POROUS MATERIALS FOR ELECTRONIC DEVICES 审中-公开
    直接形成电子设备的多孔材料

    公开(公告)号：WO2017062786A1

    公开(公告)日：2017-04-13

    申请号：PCT/US2016/056020

    申请日：2016-10-07

    Applicant: WILLIAM MARSH RICE UNIVERSITY

    Inventor： TOUR, James, M. ,  JI, Yonngsung ,  LEE, Seoung-ki

    IPC: H01L45/00 ,  H01L27/24 ,  B82Y40/00

    CPC classification number: H01L45/1625 ,  H01L27/2418 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

    Abstract: A method for forming an electronic device may comprising the steps of selecting a substrate for an electronic device, and depositing a porous film utilizing physical vapor deposition, dry deposition, evaporative deposition, e-beam evaporation, plasma enhanced chemical vapor deposition, or atomic layer deposition. In some embodiments, a deposition rate, temperature, pressure, or combination thereof may be carefully controlled during deposition to generate the porous film. Further, the depositing of the porous film occurs without the need for further processing. Additional steps may also include depositing an additional layer for the electronic device. In some case, the method may also include depositing and/or patterning a secondary electronic device on top or below the first electronic device.

    Abstract translation: 一种形成电子器件的方法可以包括以下步骤：选择用于电子器件的衬底，以及利用物理气相沉积，干法沉积，蒸发沉积，电子束蒸发，等离子体增强化学气相沉积或原子层沉积多孔膜 沉积。 在一些实施例中，沉积速率，温度，压力或其组合可以在沉积期间小心地控制以产生多孔膜。 此外，多孔膜的沉积发生，而不需要进一步加工。 附加步骤还可以包括为电子设备沉积附加层。 在一些情况下，该方法还可以包括在第一电子设备的顶部或下方沉积和/或图案化次级电子设备。

    TUNABLE VARIABLE RESISTANCE MEMORY DEVICE
    4.
    发明申请
    TUNABLE VARIABLE RESISTANCE MEMORY DEVICE 审中-公开
    可变电阻存储器件

    公开(公告)号：WO2016195763A1

    公开(公告)日：2016-12-08

    申请号：PCT/US2016/016003

    申请日：2016-02-01

    Applicant: BOISE STATE UNIVERSITY

    Inventor： CAMPBELL, Kristy, A.

    IPC: H01L45/00

    CPC classification number: H01L45/141 ,  G11C13/0069 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1625

    Abstract: A variable resistance memory device (100, 200, 300, 400) includes a first electrode (110, 210, 310) and a second electrode (160, 260, 360). The device may includes a chalcogenide glass (140, 240, 340) layer between the first electrode and the second electrode. The chalcogenide glass layer may include a chalcogenide glass material co-deposited with a metal material. The device also includes a metal ion source structure (150, 250, 350) between the chalcogenide glass layer and the second electrode. The device may include a buffer layer (120, 220) between the first electrode and the chalcogenide glass layer.

    Abstract translation: 可变电阻存储器件（100,200,300,400）包括第一电极（110,210,310）和第二电极（160,260,360）。 该装置可以包括在第一电极和第二电极之间的硫族化物玻璃（140,240,340）层。 硫族化物玻璃层可以包括与金属材料共沉积的硫族化物玻璃材料。 该装置还包括在硫族化物玻璃层和第二电极之间的金属离子源结构（150,250,350）。 该装置可以包括在第一电极和硫族化物玻璃层之间的缓冲层（120,220）。

    ELECTRON BARRIER HEIGHT CONTROLLED INTERFACES OF RESISTIVE SWITCHING LAYERS IN RESISTIVE RANDOM ACCESS MEMORY CELLS
    5.
    发明申请
    ELECTRON BARRIER HEIGHT CONTROLLED INTERFACES OF RESISTIVE SWITCHING LAYERS IN RESISTIVE RANDOM ACCESS MEMORY CELLS 审中-公开
    电阻式随机存取存储器电容栅极高度控制电阻开关层的界面

    公开(公告)号：WO2016085665A1

    公开(公告)日：2016-06-02

    申请号：PCT/US2015/060368

    申请日：2015-11-12

    Applicant: INTERMOLECULAR, INC.

    Inventor： WANG, Yun ,  NARDI, Federico

    IPC: H01L29/51

    CPC classification number: H01L45/12 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1625

    Abstract: Provided are resistive switching memory cells and method of forming such cells. A memory cell includes a resistive switching layer disposed between two buffer layers. The electron barrier height of the material used for each buffer layer is less than the electron barrier height of the material used for the resistive switching layer. Furthermore, the thickness of each buffer layer may be less than the thickness of the resistive switching layer. The buffer layers reduce diffusion between the resistive switching layer and electrodes. Furthermore, the buffer layers improve data retention and prevent unintentional resistive switching when a reading signal is applied to the memory cell. The reading signal uses a low voltage and most of the electron tunneling is blocked by the buffer layers during this operation. On the other hand, the buffer layers allow electrode tunneling at higher voltages used for forming and switching signals.

    Abstract translation: 提供了电阻式开关存储单元和形成这种单元的方法。 存储单元包括设置在两个缓冲层之间的电阻式开关层。 用于每个缓冲层的材料的电子势垒高度小于用于电阻式开关层的材料的电子势垒高度。 此外，每个缓冲层的厚度可以小于电阻式开关层的厚度。 缓冲层减少电阻式开关层和电极之间的扩散。 此外，当读取信号被施加到存储器单元时，缓冲层改善数据保持并防止无意的电阻性切换。 读取信号使用低电压，并且在该操作期间大部分电子隧道被缓冲层阻挡。 另一方面，缓冲层允许用于形成和切换信号的较高电压下的电极隧穿。

    NON-VOLATILE RESISTANCE SWITCHING DEVICES
    6.
    发明申请
    NON-VOLATILE RESISTANCE SWITCHING DEVICES 审中-公开
    非易失性电阻开关器件

    公开(公告)号：WO2015179593A1

    公开(公告)日：2015-11-26

    申请号：PCT/US2015031889

    申请日：2015-05-21

    Applicant: TRUSTEES OF THE UNVERSITY OF PENNSYLVANIA

    Inventor： CHEN I-WEI ,  LU YANG

    IPC: H01L47/00

    CPC classification number: H01L45/06 ,  H01L45/141 ,  H01L45/145 ,  H01L45/147 ,  H01L45/1625

    Abstract: The present disclosure provides, inter alia, amorphous materials useful in electronic devices such as memory devices. In some embodiments, these materials include a semiconductor having an electronegative element doped within. The present invention may b understood more readily by reference to the following detailed description taken in connection with the accompanying figures and examples, which form a part of this disclosure. It is to be understood that this invention is not limited to the specific devices, methods, applications, conditions or parameters described and/or shown herein, and that the terminology used herein is for the purpose of describing particular embodiments by way of example only and is not intended to be limiting of the claimed invention.

    Abstract translation: 本公开尤其提供了用于诸如存储器件的电子设备中的无定形材料。 在一些实施例中，这些材料包括掺杂有电负性元素的半导体。 通过参考形成本公开的一部分的附图和实施例的以下详细描述，本发明可以更容易理解。 应当理解，本发明不限于本文所描述和/或示出的具体设备，方法，应用，条件或参数，并且本文使用的术语仅用于通过示例的方式描述特定实施例， 不旨在限制所要求保护的发明。

    COMPLEMENTARY RESISTIVE SWITCHING IN SINGLE RESISTIVE MEMORY DEVICES
    9.
    发明申请
    COMPLEMENTARY RESISTIVE SWITCHING IN SINGLE RESISTIVE MEMORY DEVICES 审中-公开
    单电阻存储器件中的互补电阻开关

    公开(公告)号：WO2014025434A3

    公开(公告)日：2014-05-01

    申请号：PCT/US2013041046

    申请日：2013-05-15

    Applicant: UNIV MICHIGAN

    Inventor： LU WEI ,  YANG YUCHAO

    IPC: H01L27/115

    CPC classification number: H01L45/08 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

    Abstract: A single resistive memory device comprises a first metal oxide layer and a second metal oxide layer. The second metal oxide layer is located underneath the first metal oxide layer, and has a different stoichiometry than the second metal oxide layer. In embodiment, the first and second metal oxide layers each comprise different oxides of the same base metal, and the base metal may comprise tantalum. An article of manufacture comprising a single resistive memory device that is operable in a complementary resistive switching mode is also provided.

    Abstract translation: 单电阻存储器件包括第一金属氧化物层和第二金属氧化物层。 第二金属氧化物层位于第一金属氧化物层下方，并具有与第二金属氧化物层不同的化学计量比。 在实施例中，第一和第二金属氧化物层各自包含相同基底金属的不同氧化物，并且基底金属可以包括钽。 还提供了包括可在互补电阻切换模式下操作的单个电阻式存储器装置的制品。

Patent Agency Ranking