公开(公告)号：WO2017184300A3

公开(公告)日：2017-10-26

申请号：PCT/US2017/024319

申请日：2017-03-27

申请人： QUALCOMM INCORPORATED

发明人： SAHU, Satyanarayana ,  GUPTA, Vinod ,  CHEN, Xiangdong ,  RACHAPALLI, Triveni

IPC分类号： H01L27/118 ,  H01L27/02 ,  H01L29/66 ,  H01L27/092 ,  G06F17/50 ,  H01L23/528

摘要： In an aspect of the disclosure, apparatuses for reducing the cost of using an ECO standard cell library in chip design are provided. Such an apparatus is a MOS device including several regions (102, 104, 106, 108). The MOS device includes a first pMOS transistor (192) and a first nMOS transistor (194) in a first region (102) of the device, each of the transistors having fins. The pMOS transistor gate of the first pMOS transistor and the nMOS transistor gate of the first nMOS transistor are formed by a gate interconnect (112) extending in a first direction across the device. The MOS device includes several unutilized pMOS and nMOS transistors in a second region (104) of the device adjacent to the first region. Fins of the pMOS and nMOS transistors in the first region are disconnected from fins of the unutilized pMOS and nMOS transistors in the second region.

摘要翻译： 在本公开的一个方面中，提供了用于降低在芯片设计中使用ECO标准单元库的成本的装置。 这种装置是包括几个区域（102,104,106,108）的MOS器件。 MOS器件包括在器件的第一区域（102）中的第一pMOS晶体管（192）和第一nMOS晶体管（194），每个晶体管具有鳍片。 第一pMOS晶体管的pMOS晶体管栅极和第一nMOS晶体管的nMOS晶体管栅极由跨设备的第一方向延伸的栅极互连（112）形成。 MOS器件在与第一区域相邻的器件的第二区域（104）中包括若干未使用的pMOS和nMOS晶体管。 第一区域中的pMOS和nMOS晶体管的鳍与第二区域中未使用的pMOS和nMOS晶体管的鳍片断开。

公开(公告)号：WO2017172148A3

公开(公告)日：2017-10-05

申请号：PCT/US2017/019470

申请日：2017-02-24

申请人： QUALCOMM INCORPORATED

发明人： CHEN, Xiangdong ,  BOYNAPALLI, Venugopal ,  SAHU, Satyanarayana ,  LIM, Hyeokjin ,  GUPTA, Mukul

IPC分类号： H01L27/02 ,  H01L27/118

摘要： A standard cell IC includes pMOS transistors in a pMOS region (316) of a MOS device and nMOS transistors in an nMOS region (318) of the MOS device. The pMOS and nMOS regions extend between a first cell edge (304a) and a second cell edge (304b). The standard cell IC further includes at least one single diffusion break (312) located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion (314') at the first cell edge (304a) and a second double diffusion break portion (314) at the second cell edge (304b).

公开(公告)号：WO2017204928A1

公开(公告)日：2017-11-30

申请号：PCT/US2017/027968

申请日：2017-04-17

申请人： QUALCOMM INCORPORATED

发明人： SAHU, Satyanarayana ,  RAJ, Satish ,  CHANDRASEKARAN, Shiva Ram ,  QIU, Li ,  TYAGI, Arun ,  PHILIP, Mathew ,  VERMA, Rajesh

IPC分类号： G06F1/32

摘要： A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.

摘要翻译： 半导体器件包括：具有多个子核心的处理核心，从所述多个子核心的第一子核心跨越至第二子核心的多个电力轨道，所述多个电力 被配置为向所述第一子核和所述第二子核中的每一个提供工作电压的轨道以及限定所述第一子核和所述第二子核之间的边界的多个单元，所述单元中的每一个在相应的功率中提供不连续性 轨道，其中不连续性包括在半导体器件的多于一层中的相应功率轨中的中断。

公开(公告)号：WO2017172148A2

公开(公告)日：2017-10-05

申请号：PCT/US2017/019470

申请日：2017-02-24

申请人： QUALCOMM INCORPORATED

发明人： CHEN, Xiangdong ,  BOYNAPALLI, Venugopal ,  SAHU, Satyanarayana ,  LIM, Hyeokjin ,  GUPTA, Mukul

IPC分类号： H01L27/02 ,  H01L27/118

摘要： A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.

摘要翻译： 标准单元IC包括MOS器件的pMOS区域中的pMOS晶体管。 pMOS区域在第一单元边缘和与第一单元边缘相对的第二单元边缘之间延伸。 标准单元IC还包括MOS器件的nMOS区域中的nMOS晶体管。 nMOS区域在第一单元边缘和第二单元边缘之间延伸。 标准单元IC还包括位于第一单元边缘与第二单元边缘之间的内部区域中的至少一个单个扩散中断，所述内部区域延伸穿过pMOS区域和nMOS区域以将pMOS区域分成pMOS子区域并且将nMOS区域分成 nMOS次区域。 标准单元IC包括在第一单元边缘处的第一双扩散中断部分。 标准单元IC还包括在第二单元边缘的第二个双扩散中断部分。

公开(公告)号：WO2018013695A1

公开(公告)日：2018-01-18

申请号：PCT/US2017/041721

申请日：2017-07-12

申请人： QUALCOMM INCORPORATED

发明人： SAHU, Satyanarayana ,  CHEN, Xiangdong ,  VILANGUDIPITCHAI, Ramaprasath ,  KUMAR, Dorav

IPC分类号： H01L27/02 ,  H01L27/118 ,  H01L27/092 ,  H03K19/177 ,  H03K19/00 ,  H03K19/003

摘要： A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.

摘要翻译： 标准单元IC可以包括多个pMOS晶体管，每个pMOS晶体管包括pMOS晶体管漏极，pMOS晶体管源极和pMOS晶体管栅极。 多个pMOS晶体管中的每个pMOS晶体管漏极和pMOS晶体管源极可以耦合到第一电压源。 标准单元IC还可以包括多个nMOS晶体管，每个nMOS晶体管包括nMOS晶体管漏极，nMOS晶体管源极和nMOS晶体管栅极。 多个nMOS晶体管中的每个nMOS晶体管漏极和nMOS晶体管源极耦合到比第一电压源低的第二电压源。

公开(公告)号：WO2017048532A1

公开(公告)日：2017-03-23

申请号：PCT/US2016/050072

申请日：2016-09-02

申请人： QUALCOMM INCORPORATED

发明人： SAHU, Satyanarayana ,  HIREMATH, Renukprasad, Shreedhar ,  GUTTAL, Radhika, Vinayak

IPC分类号： H01L27/02 ,  G06F17/50 ,  H01L23/525 ,  H01L23/528 ,  H01L27/118

CPC分类号： G06F17/5068 ,  H01L23/525 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

摘要： Hybrid diffusion standard library cells for engineering change orders (ECO), and related systems and methods are disclosed. The hybrid diffusion standard library cells may be fabricated with reduced costs because masks corresponding to fixed base layers remain constant across integrated circuit (IC) devices. The hybrid diffusion standard library cell includes at least one transistor and multiple diffusion regions (102(1-4)), wherein a break region (104) separates at least two of the multiple diffusion regions. The hybrid diffusion standard library cell includes one or more MEOL interconnects (106(1-19)) at fixed locations that are configured to connect transistors to a first metal layer. One of the interconnects (106(17)) may be disposed in the break region. Including the break region between multiple diffusion regions helps to limit the locations of the fixed MEOL interconnects, which limits possible locations for base level transistors and fixes the base layer design.

摘要翻译： 公开了用于工程变更单（ECO）的混合扩散标准库单元及相关系统和方法。 可以以降低的成本制造混合扩散标准库单元，因为对应于固定基极层的掩模在集成电路（IC）器件上保持恒定。 混合扩散标准库单元包括至少一个晶体管和多个扩散区域（102（1-4）），其中断开区域（104）分离多个扩散区域中的至少两个。 混合扩散标准库单元包括在被配置为将晶体管连接到第一金属层的固定位置处的一个或多个MEOL互连（106（1-19））。 互连（106（17））之一可以设置在断开区域中。 包括多个扩散区域之间的断开区域有助于限制固定的MEOL互连的位置，这限制了基极晶体管的可能位置并固定了基极层设计。

公开(公告)号：WO2016204866A1

公开(公告)日：2016-12-22

申请号：PCT/US2016/029392

申请日：2016-04-26

申请人： QUALCOMM INCORPORATED

发明人： SAHU, Satyanarayana ,  HIREMATH, Renukprasad Shreedhar ,  GUTTAL, Radhika Vinayak

IPC分类号： H01L27/02 ,  H02H9/04

CPC分类号： H01L27/0266 ,  H01L27/092

摘要： A MOS device for reducing an antenna effect is provided. The MOS device includes a diode including a first nMOS transistor having a first nMOS transistor source, a first nMOS transistor drain, a first nMOS transistor gate, and an nMOS transistor body. The nMOS transistor body is coupled to a first voltage source and is an anode of the diode. The first nMOS transistor source, the first nMOS transistor drain, and the first nMOS transistor gate are coupled together and are a cathode of the diode. The MOS device further includes an interconnect extending between a driver output and a load input. The interconnect is coupled to the cathode of the diode. The interconnect may extend on one metal layer only between the driver output and the load input.

摘要翻译： 提供了用于降低天线效应的MOS器件。 MOS器件包括二极管，其包括具有第一nMOS晶体管源极，第一nMOS晶体管漏极，第一nMOS晶体管栅极和nMOS晶体管本体的第一nMOS晶体管。 nMOS晶体管体耦合到第一电压源并且是二极管的阳极。 第一nMOS晶体管源，第一nMOS晶体管漏极和第一nMOS晶体管栅极耦合在一起，并且是二极管的阴极。 MOS器件还包括在驱动器输出和负载输入之间延伸的互连。 互连件耦合到二极管的阴极。 互连可以仅在驱动器输出和负载输入之间的一个金属层上延伸。

公开(公告)号：WO2018125546A1

公开(公告)日：2018-07-05

申请号：PCT/US2017/065429

申请日：2017-12-08

申请人： QUALCOMM INCORPORATED

发明人： SAHU, Satyanarayana ,  CHEN, Xiangdong ,  BOYNAPALLI, Venugopal ,  LIM, Hyeokjin ,  MALABRY, Mickael ,  GUPTA, Mukul

IPC分类号： H01L27/02 ,  H01L23/528 ,  H01L27/118

摘要： A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mx layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second M x layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second M x layer interconnects are parallel. The MOS device further includes a first M x+1 layer interconnect extending in a second direction orthogonal to the first direction. The first M x+1 layer interconnect is coupled to the first M x layer interconnect and the second M x layer interconnect. The MOS device further includes a second M x+1 layer interconnect extending in the second direction. The second M x+1 layer interconnect is coupled to the first M x layer interconnect and the second M x layer interconnect. The second M x+1 layer interconnect is parallel to the first M x+1 layer interconnect.

公开(公告)号：WO2017218360A1

公开(公告)日：2017-12-21

申请号：PCT/US2017/036865

申请日：2017-06-09

申请人： QUALCOMM INCORPORATED

发明人： CHEN, Xiangdong ,  LIM, Hyeokjin Bruce ,  SAHU, Satyanarayana ,  BOYNAPALLI, Venugopal

IPC分类号： H01L27/02 ,  H01L23/528 ,  H01L27/118

CPC分类号： H01L29/0646 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

摘要： A MOS IC (300) includes a first contact interconnect (330) in a first standard cell (302a) that extends in a first direction and contacts a first MOS transistor source (310) and a voltage source (342). Still further, the MOS IC includes a first double diffusion break extending along a first boundary (344) in the first direction of the first standard cell and a second standard cell (302b). The MOS IC also includes a second contact interconnect (360) extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect is within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC includes a third contact interconnect (362) extending in a second direction orthogonal to the first direction and coupling the first contact interconnect and the second contact interconnect together.

摘要翻译： MOS IC（300）包括在第一标准单元（302a）中的第一接触互连（330），其在第一方向上延伸并接触第一MOS晶体管源极（310）和电压源 （342）。 另外，MOS IC包括沿着第一标准单元的第一方向上的第一边界（344）和第二标准单元（302b）延伸的第一双扩散中断。 MOS IC还包括在第一双扩散分裂的一部分上延伸的第二接触互连（360）。 在一个方面，第二接触互连在第一标准单元和第二标准单元两者内并耦合到电压源。 此外，MOS IC包括在与第一方向正交的第二方向上延伸并且将第一接触互连和第二接触互连耦合在一起的第三接触互连（362）。

公开(公告)号：WO2017184300A2

公开(公告)日：2017-10-26

申请号：PCT/US2017/024319

申请日：2017-03-27

申请人： QUALCOMM INCORPORATED

发明人： SAHU, Satyanarayana ,  GUPTA, Vinod ,  CHEN, Xiangdong ,  RACHAPALLI, Triveni

IPC分类号： H01L27/118 ,  H01L27/02 ,  H01L29/66 ,  H01L27/092 ,  G06F17/50 ,  H01L23/528

CPC分类号： H01L27/0207 ,  G06F17/5077 ,  H01L23/5283 ,  H01L27/0924 ,  H01L27/11807 ,  H01L28/00 ,  H01L2027/11831

摘要： In an aspect of the disclosure, apparatuses for reducing the cost of using an ECO standard cell library in chip design are provided. Such an apparatus may be a MOS device including several regions. The MOS device may include a pMOS transistor and an nMOS transistor in a first region of the device. The pMOS transistor gate of the pMOS transistor and the nMOS transistor gate of the nMOS transistor may be formed by a gate interconnect extending in a first direction across the device. The MOS device may include several unutilized pMOS transistors and several unutilized nMOS transistors in a second region of the device adjacent to the first region. Fins of the pMOS transistors and the nMOS transistors in the first region may be disconnected from fins of the unutilized pMOS transistors and the unutilized nMOS transistors in the second region.

摘要翻译： 在本公开的一个方面中，提供了用于降低在芯片设计中使用ECO标准单元库的成本的装置。 这种装置可以是包括几个区域的MOS器件。 MOS器件可以在器件的第一区域中包括pMOS晶体管和nMOS晶体管。 pMOS晶体管的pMOS晶体管栅极和nMOS晶体管的nMOS晶体管栅极可以由沿着穿过器件的第一方向延伸的栅极互连形成。 MOS器件可以包括若干未使用的pMOS晶体管和在与第一区域相邻的器件的第二区域中的若干未使用的nMOS晶体管。 第一区域中的pMOS晶体管和nMOS晶体管的鳍可以与未使用的pMOS晶体管的鳍和第二区中的未使用的nMOS晶体管断开。