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    A NOVEL STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF
    1.
    发明申请
    A NOVEL STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF 审中-公开

    公开(公告)号：WO2019152093A1

    公开(公告)日：2019-08-08

    申请号：PCT/US2018/064371

    申请日：2018-12-07

    申请人： QUALCOMM INCORPORATED

    发明人： CHEN, Xiangdong ,  BOYNAPALLI, Venugopal ,  LIM, Hyeokjin

    IPC分类号： H01L27/02 ,  H01L27/118

    摘要： According to certain aspects of the present disclosure, a chip includes a first gate, a second gate, a first source, a first source contact disposed on the first source, a metal interconnect above the first source contact and the first gate, a first gate contact electrically coupling the first gate to the metal interconnect, and a first via electrically coupling the first source contact to the metal interconnect. The chip also includes a power rail, and a second via electrically coupling the first source contact to the power rail. The second gate is between the first source and the first gate, and the metal interconnect passes over the second gate.

    V1 AND HIGHER LAYERS PROGRAMMABLE ECO STANDARD CELLS
    3.
    发明申请
    V1 AND HIGHER LAYERS PROGRAMMABLE ECO STANDARD CELLS 审中-公开
    V1和更高层可编程生态标准细胞

    公开(公告)号：WO2017184300A3

    公开(公告)日：2017-10-26

    申请号：PCT/US2017/024319

    申请日：2017-03-27

    申请人： QUALCOMM INCORPORATED

    发明人： SAHU, Satyanarayana ,  GUPTA, Vinod ,  CHEN, Xiangdong ,  RACHAPALLI, Triveni

    IPC分类号： H01L27/118 ,  H01L27/02 ,  H01L29/66 ,  H01L27/092 ,  G06F17/50 ,  H01L23/528

    摘要： In an aspect of the disclosure, apparatuses for reducing the cost of using an ECO standard cell library in chip design are provided. Such an apparatus is a MOS device including several regions (102, 104, 106, 108). The MOS device includes a first pMOS transistor (192) and a first nMOS transistor (194) in a first region (102) of the device, each of the transistors having fins. The pMOS transistor gate of the first pMOS transistor and the nMOS transistor gate of the first nMOS transistor are formed by a gate interconnect (112) extending in a first direction across the device. The MOS device includes several unutilized pMOS and nMOS transistors in a second region (104) of the device adjacent to the first region. Fins of the pMOS and nMOS transistors in the first region are disconnected from fins of the unutilized pMOS and nMOS transistors in the second region.

    摘要翻译： 在本公开的一个方面中，提供了用于降低在芯片设计中使用ECO标准单元库的成本的装置。 这种装置是包括几个区域（102,104,106,108）的MOS器件。 MOS器件包括在器件的第一区域（102）中的第一pMOS晶体管（192）和第一nMOS晶体管（194），每个晶体管具有鳍片。 第一pMOS晶体管的pMOS晶体管栅极和第一nMOS晶体管的nMOS晶体管栅极由跨设备的第一方向延伸的栅极互连（112）形成。 MOS器件在与第一区域相邻的器件的第二区域（104）中包括若干未使用的pMOS和nMOS晶体管。 第一区域中的pMOS和nMOS晶体管的鳍与第二区域中未使用的pMOS和nMOS晶体管的鳍片断开。

    CROSS-COUPLED CLOCK SIGNAL DISTRIBUTION LAYOUT IN MULTI-HEIGHT SEQUENTIAL CELLS FOR UNI-DIRECTIONAL M1
    4.
    发明申请
    CROSS-COUPLED CLOCK SIGNAL DISTRIBUTION LAYOUT IN MULTI-HEIGHT SEQUENTIAL CELLS FOR UNI-DIRECTIONAL M1 审中-公开
    用于单向M1的多重顺序细胞中的交叉耦合时钟信号分布布局

    公开(公告)号：WO2016190958A1

    公开(公告)日：2016-12-01

    申请号：PCT/US2016/025388

    申请日：2016-03-31

    申请人： QUALCOMM INCORPORATED

    发明人： GUPTA, Mukul ,  CHEN, Xiangdong ,  KWON, Ohsang

    IPC分类号： H01L27/02 ,  H01L23/528 ,  H01L27/118 ,  G06F1/10 ,  G06F17/50

    CPC分类号： H01L23/528 ,  G06F1/10 ,  G06F17/5068 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11879

    摘要： A MOS device includes first, second, third, and fourth interconnects. The first interconnect (402) extends on a first track in a first direction. The first interconnect is configured in a metal layer. The second interconnect (404) extends on the first track in the first direction. The second interconnect is configured in the metal layer. The third interconnect (408) extends on a second track in the first direction. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. The second and third interconnects (404. 408) are configured to provide a first signal (Clk). The fourth interconnect (410) extends on the second track in the first direction. The fourth interconnect is configured in the metal layer. The fourth interconnect is coupled to the first interconnect. The first and fourth interconnects (402, 410) are configured to provide a second signal (Clk) different than the first signal.

    摘要翻译： MOS器件包括第一，第二，第三和第四互连。 第一互连（402）在第一方向上在第一轨道上延伸。 第一互连配置在金属层中。 第二互连（404）在第一方向上在第一轨道上延伸。 第二互连配置在金属层中。 第三互连（408）在第一方向上的第二轨道上延伸。 第三互连配置在金属层中。 第二条轨道平行于第一条轨道。 第三互连耦合到第二互连。 第二和第三互连（404.408）被配置为提供第一信号（Clk）。 第四互连（410）在第一方向上在第二轨道上延伸。 第四互连配置在金属层中。 第四互连耦合到第一互连。 第一和第四互连（402,410）被配置为提供与第一信号不同的第二信号（Clk）。

    CONDUCTIVE LAYER ROUTING
    5.
    发明申请
    CONDUCTIVE LAYER ROUTING 审中-公开
    导电层路由

    公开(公告)号：WO2015102753A1

    公开(公告)日：2015-07-09

    申请号：PCT/US2014/065529

    申请日：2014-11-13

    申请人： QUALCOMM INCORPORATED

    发明人： SONG, Stanley Seungchul ,  RIM, Kern ,  WANG, Zhongze ,  XU, Jeffrey Junhao ,  CHEN, Xiangdong ,  YEAP, Choh Fei

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76802 ,  H01L21/76814 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask (500) across active contacts (112) to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts (112-5) and selectively insulate some of the active contacts (112-2). The method also includes depositing a conductive material (1100) on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.

    摘要翻译： 制造中间线（MOL）层和包括MOL层的器件的方法。 根据本公开的一个方面的方法包括将半导体衬底的半导体器件的端子上的有源触点（112）沉积硬掩模（500）。 这种方法还包括图案化硬掩模以选择性地暴露一些有源触点（112-5）并且选择性地绝缘一些有源触点（112-2）。 该方法还包括在图案化的硬掩模和暴露的有源触点上沉积导电材料（1100），以在半导体器件的有效区域上将暴露的有源触点彼此耦合。

    A METAL OXIDE SEMICONDUCTOR CELL DEVICE ARCHITECTURE WITH MIXED DIFFUSION BREAK ISOLATION TRENCHES
    6.
    发明申请
    A METAL OXIDE SEMICONDUCTOR CELL DEVICE ARCHITECTURE WITH MIXED DIFFUSION BREAK ISOLATION TRENCHES 审中-公开
    具有混合扩散隔离栅的金属氧化物半导体器件结构

    公开(公告)号：WO2017172148A2

    公开(公告)日：2017-10-05

    申请号：PCT/US2017/019470

    申请日：2017-02-24

    申请人： QUALCOMM INCORPORATED

    发明人： CHEN, Xiangdong ,  BOYNAPALLI, Venugopal ,  SAHU, Satyanarayana ,  LIM, Hyeokjin ,  GUPTA, Mukul

    IPC分类号： H01L27/02 ,  H01L27/118

    摘要： A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.

    摘要翻译： 标准单元IC包括MOS器件的pMOS区域中的pMOS晶体管。 pMOS区域在第一单元边缘和与第一单元边缘相对的第二单元边缘之间延伸。 标准单元IC还包括MOS器件的nMOS区域中的nMOS晶体管。 nMOS区域在第一单元边缘和第二单元边缘之间延伸。 标准单元IC还包括位于第一单元边缘与第二单元边缘之间的内部区域中的至少一个单个扩散中断，所述内部区域延伸穿过pMOS区域和nMOS区域以将pMOS区域分成pMOS子区域并且将nMOS区域分成 nMOS次区域。 标准单元IC包括在第一单元边缘处的第一双扩散中断部分。 标准单元IC还包括在第二单元边缘的第二个双扩散中断部分。

    HIGH PERFORMANCE STANDARD CELL
    7.
    发明申请
    HIGH PERFORMANCE STANDARD CELL 审中-公开
    高性能标准电池

    公开(公告)号：WO2015134202A1

    公开(公告)日：2015-09-11

    申请号：PCT/US2015/016690

    申请日：2015-02-19

    申请人： QUALCOMM INCORPORATED

    发明人： CHEN, Xiangdong ,  KWON, Ohsang ,  VANG, Foua ,  DATTA, Animesh ,  RASOULI, Seid Hadi

    IPC分类号： H01L27/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/118

    CPC分类号： H01L27/0207 ,  H01L21/76895 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/11807 ,  H01L2027/11831 ,  H01L2027/11861 ,  H01L2027/11866

    摘要： A transistor cell is provided that includes a continuous oxide definition (OD) region defined in a substrate; a gate (450) for a transistor between a first dummy gate (425) and a second dummy gate (430), wherein a source for the transistor is defined in a first portion of the OD region between the gate and the first dummy gate, and wherein a drain for the transistor is defined in a second portion of the OD region between the gate and a first side of the second dummy gate; a first gate-directed local interconnect (470) and a first diffusion- directed local interconnect (440) couple a third portion of the OD region adjacent a second opposing side of the second dummy gate and the second dummy gate to a source voltage.

    摘要翻译： 提供晶体管单元，其包括限定在衬底中的连续氧化物界定（OD）区域; 在第一虚拟栅极（425）和第二虚拟栅极（430）之间的晶体管的栅极（450），其中晶体管的源极限定在栅极和第一伪栅极之间的OD区域的第一部分中， 并且其中所述晶体管的漏极限定在所述栅极与所述第二虚拟栅极的第一侧之间的所述OD区域的第二部分中; 第一栅极定向局部互连（470）和第一扩散导向局部互连（440）将邻近第二伪栅极和第二虚设栅极的第二相对侧的OD区域的第三部分耦合到源极电压。

    PLACEMENT METHODOLOGY TO REMOVE FILLER
    9.
    发明申请
    PLACEMENT METHODOLOGY TO REMOVE FILLER 审中-公开

    公开(公告)号：WO2019112740A1

    公开(公告)日：2019-06-13

    申请号：PCT/US2018/059530

    申请日：2018-11-07

    申请人： QUALCOMM INCORPORATED

    发明人： CHEN, Xiangdong ,  DOBRE, Sorin Adrian ,  LIM, Hyeokjin ,  BOYNAPALLI, Venugopal

    IPC分类号： H01L27/02 ,  G06F17/50 ,  H01L27/118

    摘要： In certain aspects, a semiconductor die includes a first cell and a second cell. The first cell includes first transistors, and a first interconnect structure interconnecting the first transistors to form a first circuit. The second cell includes second transistors, and a second interconnect structure interconnecting the second transistors to form a second circuit. The first circuit and the second circuit are configured to perform a same function, and a length of the first cell in a first lateral direction is greater than a length of the second cell in the first lateral direction.

    A STANDARD CELL ARCHITECTURE FOR REDUCED LEAKAGE CURRENT AND IMPROVED DECOUPLING CAPACITANCE
    10.
    发明申请
    A STANDARD CELL ARCHITECTURE FOR REDUCED LEAKAGE CURRENT AND IMPROVED DECOUPLING CAPACITANCE 审中-公开
    标准单元架构，降低泄漏电流和改善解耦电容

    公开(公告)号：WO2018013695A1

    公开(公告)日：2018-01-18

    申请号：PCT/US2017/041721

    申请日：2017-07-12

    申请人： QUALCOMM INCORPORATED

    发明人： SAHU, Satyanarayana ,  CHEN, Xiangdong ,  VILANGUDIPITCHAI, Ramaprasath ,  KUMAR, Dorav

    IPC分类号： H01L27/02 ,  H01L27/118 ,  H01L27/092 ,  H03K19/177 ,  H03K19/00 ,  H03K19/003

    摘要： A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.

    摘要翻译： 标准单元IC可以包括多个pMOS晶体管，每个pMOS晶体管包括pMOS晶体管漏极，pMOS晶体管源极和pMOS晶体管栅极。 多个pMOS晶体管中的每个pMOS晶体管漏极和pMOS晶体管源极可以耦合到第一电压源。 标准单元IC还可以包括多个nMOS晶体管，每个nMOS晶体管包括nMOS晶体管漏极，nMOS晶体管源极和nMOS晶体管栅极。 多个nMOS晶体管中的每个nMOS晶体管漏极和nMOS晶体管源极耦合到比第一电压源低的第二电压源。