公开(公告)号：WO2022103539A1

公开(公告)日：2022-05-19

申请号：PCT/US2021/054406

申请日：2021-10-11

Applicant: QUALCOMM INCORPORATED

Inventor： YIN, Wen ,  AN, Yonghao ,  ALDRETE, Manuel

IPC: H01L23/498

Abstract: Disclosed is a package and method of forming the package with a mixed pad size. The package includes a first set of pads having a first size and a first pitch, where the first set of pads are solder mask defined (SMD) pads. The package also includes a second set of pads having a second size and a second pitch, where the second set of pads are nonsolder mask defined (NSMD) pads.

公开(公告)号：WO2023048882A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/041235

申请日：2022-08-23

Applicant: QUALCOMM INCORPORATED

Inventor： FENG, Chien-Te ,  YIN, Wen ,  SALMON, Jay Scott

IPC: H01L25/16 ,  H01L23/36 ,  H01L23/552 ,  H01L23/00

Abstract: A device comprising a package and a board. The package includes a substrate comprising a first surface and a second surface, a passive component coupled to the first surface of the substrate, an integrated device coupled to the second surface of the substrate, a back side metal layer coupled to a back side of the integrated device, a first solder interconnect coupled to the back side metal layer, and a plurality of solder interconnects coupled to the second surface of the substrate. The board is coupled to the package through the plurality of solder interconnects. The first solder interconnect is coupled to the board.

公开(公告)号：WO2022182461A2

公开(公告)日：2022-09-01

申请号：PCT/US2022/013697

申请日：2022-01-25

Applicant: QUALCOMM INCORPORATED

Inventor： HU, Wei ,  HE, Dongming ,  YIN, Wen ,  GUAN, Zhe ,  ZHAO, Lily

IPC: H01L23/485 ,  H01L21/60 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/11622 ,  H01L2224/118 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13171 ,  H01L2224/13565 ,  H01L2224/13584 ,  H01L2224/13624 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/13686 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2924/3651 ,  H01L2924/381 ,  H01L2924/3841

Abstract: An IC package (900A-E) includes a substrate (920) and an integrated circuit (IC) structure comprising a die (410, 510, 610, 710, 810) (e.g., a flip-chip (FC) die) and one or more die interconnects (430) to electrically couple the die (410, 510, 610, 710, 810) to the substrate (920). The die interconnect (430) includes a pillar (440, 540, 640, 740, 840), a wetting barrier (460, 560, 660, 760, 860) on the pillar (440, 540, 640, 740, 840), and a solder cap (450, 550, 650, 750, 850) on the wetting barrier (460, 560, 660, 760, 860). The wetting barrier (460, 560, 660, 760, 860) is wider than the pillar (440, 540, 640, 740, 840), such that, during solder reflow, solder wetting of sidewall of the pillar (440, 540, 640, 740, 840) is minimised or prevented altogether. The width of the wetting barrier (460, 560, 660, 760, 860) may be greater than a width of the solder cap (450, 550, 650, 750, 850). The die interconnect (430) may also include a low wetting layer (470, 570, 770, 870) formed on at least a portion of a surface of the wetting barrier (460, 560, 760, 860) not covered by the pillar (440, 540, 740, 840), which can further mitigate solder wetting problems. The low wetting layer (470, 570, 770, 870) may have a lower solderability than the pillar (440, 540, 740, 840), for example, it may be made from metals such as Ni, Al, Cr, etc. The pillar (440, 540, 740) and the wetting barrier (460, 560, 760) may be formed from a same conductive material (e.g., Cu). Alternatively, the pillar (440) and the wetting barrier (460) may be formed from different conductive materials, with the material of the wetting barrier (460) (e.g., Ni) selected so as to also provide a chemical barrier to solder wetting on sidewalls of the pillar (440) (e.g., Cu). The IC structure may further comprise a contact layer (e.g., Ni) (780) in between the wetting barrier (760) and the solder cap (750). Alternatively, the low wetting layer (570, 870) may also be formed in between the wetting barrier (560, 860) and the solder cap (550, 850), wherein the pillar (840) may further be a first pillar, the IC structure further comprising a second pillar (890) (e.g., Cu) on the low wetting layer (870) and a contact layer (e.g., Ni) (880) between the second pillar (890) and the solder cap (850).

公开(公告)号：WO2022026064A1

公开(公告)日：2022-02-03

申请号：PCT/US2021/037000

申请日：2021-06-11

Applicant: QUALCOMM INCORPORATED

Inventor： YIN, Wen ,  AN, Yonghao ,  ALVARADO, Reynante Tamunan

IPC: H01L23/367 ,  H01L23/49 ,  H01L21/48 ,  H01L21/683 ,  H01L23/48 ,  H01L23/552 ,  H01L23/66 ,  H01L25/065 ,  H01L25/10

Abstract: A package that includes a substrate (202), an integrated device (206), a plurality of first wire bonds (210), at least one second wire bond (212), and an encapsulation layer (208). The integrated device (206) is coupled to the substrate (202). The plurality of first wire bonds (210) is coupled to the integrated device (206) and the substrate (220). The plurality of first wire bonds (210) is configured to provide at least one electrical path between the integrated device (206) and the substrate (202). The at least one second wire bond (212) is coupled to the integrated device (206). The at least one second wire bond (212) is configured to be free of an electrical connection with a circuit of the integrated device (206). The encapsulation layer (208) is located over the substrate (202) and the integrated device (206). The encapsulation layer (208) encapsulates the integrated device (206), the plurality of first wire bonds (210) and the at least one second wire bond (212). A metal layer (230) may be coupled to the outer surface of the encapsulation layer (208) and/or the side surface of the substrate (202). The metal layer (230) may be configured as an electromagnetic interference shield.