公开(公告)号：WO2008117921A1

公开(公告)日：2008-10-02

申请号：PCT/KR2008/000145

申请日：2008-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KONG, Jun Jin ,  PARK, Sung Chung ,  KANG, Dongku ,  CHAE, Dong Hyuk ,  LEE, Seung Jae ,  JO, Nam Phil ,  SONG, Seung-Hwan

IPC: G11C29/42

CPC classification number: G11C29/42 ,  G06F11/1068 ,  G11C11/5628 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.

Abstract translation: 提供各种读取级别控制装置和方法。 在各种实施例中，读取电平控制装置可以包括用于对从存储单元读取的数据进行ECC解码的错误控制码（ECC）解码单元和用于基于ECC解码数据监视误码率（BER）的监视单元，以及 读数据。 该装置还可以包括用于基于所监视的BER确定读取数据的错误率的错误确定单元，以及用于基于错误率来控制存储单元的读取电平的电平控制单元。

公开(公告)号：WO2009102100A1

公开(公告)日：2009-08-20

申请号：PCT/KR2008/004969

申请日：2008-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHO, Kyoung Lae ,  YU, Donghun ,  CHAE, Dong Hyuk ,  KONG, Jun Jin ,  KIM, Jae Hong ,  SONG, Seung-Hwan

IPC: G11C16/34

CPC classification number: G11C7/1006 ,  G11C7/14 ,  G11C11/5642 ,  G11C29/00 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50 ,  G11C2211/5634

Abstract: Example embodiments may relate to a method and an apparatus for reading data stored in a memory, for example, providing a method and an apparatus for controlling a reference voltage based on an error of the stored data. Example embodiments may provide a memory data detecting apparatus including a first voltage comparator to compare a threshold voltage of a memory cell with a first reference voltage, a first data determiner to determine a value of at least one data bit stored in the memory cell according to a result of the comparison, an error verifier to verify whether an error occurs in the determined value, a reference voltage determiner to determine a second reference voltage that is lower than the first reference voltage based on a result of the verification, and a second data determiner to re-determine the value of the data based on the determined second reference voltage.

Abstract translation: 示例性实施例可以涉及用于读取存储在存储器中的数据的方法和装置，例如提供一种基于存储的数据的错误来控制参考电压的方法和装置。 示例性实施例可以提供一种存储器数据检测装置，其包括用于将存储器单元的阈值电压与第一参考电压进行比较的第一电压比较器，第一数据确定器，用于根据存储器单元存储的至少一个数据位的值，根据 比较结果，用于验证在所确定的值中是否发生错误的错误验证器，基于验证结果确定低于第一参考电压的第二参考电压的参考电压确定器，以及第二数据 确定器，以基于所确定的第二参考电压重新确定数据的值。

公开(公告)号：WO2009022771A1

公开(公告)日：2009-02-19

申请号：PCT/KR2008/000165

申请日：2008-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SONG, Seung-Hwan ,  KONG, Jun Jin ,  PARK, Sung Chung ,  EUN, Heeseok ,  CHAE, Dong Hyuk ,  CHO, Kyoung Lae

IPC: G11C16/10

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641

Abstract: Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus may include: a first programming unit that stores data corresponding to a number of first bits in at least one first memory cell that may be connected to at least one first bit line; and a second programming unit that stores data corresponding to a number of second bits in at least one second memory cell that may be connected to at least one second bit line. Through this, it may be possible to improve data reliability and increase a number of bits to be stored in the entire memory cell.

Abstract translation: 提供了多位编程设备和方法。 一种多位编程设备可以包括：第一编程单元，其存储对应于可连接到至少一个第一位线的至少一个第一存储器单元中的多个第一位的数据; 以及第二编程单元，其将可能连接到至少一个第二位线的至少一个第二存储器单元中的与第二位数相对应的数据存储。 由此，可以提高数据可靠性并增加要存储在整个存储单元中的位数。

公开(公告)号：WO2008136568A1

公开(公告)日：2008-11-13

申请号：PCT/KR2008/000026

申请日：2008-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BYUN, Sung-Jae ,  CHAE, Dong Hyuk ,  CHO, Kyoung Lae ,  KONG, Jun Jin ,  LEE, Young Hwan ,  LEE, Seung Jae ,  JO, Nam Phil ,  KANG, Dongku

IPC: G11C16/10

CPC classification number: G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5641

Abstract: A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells.

Abstract translation: 提供了一种用于非易失性存储器的多位编程设备和方法。 在一个示例实施例中，多位编程设备可以包括多位编程单元，其被配置为将原始多位数据多位地编程到存储单元阵列中的目标存储单元;以及备份编程单元，被配置为选择备份 相对于原始多位数据的每个位存储单元阵列中的存储器单元，以及将原始多位数据的每个位编程到所选择的备份存储器单元中的相应一个。

公开(公告)号：WO2009104843A1

公开(公告)日：2009-08-27

申请号：PCT/KR2008/004531

申请日：2008-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHO, Kyoung Lae ,  KIM, Jae Hong ,  PARK, Yoon Dong ,  KONG, Jun Jin ,  CHAE, Dong Hyuk

IPC: G11C16/04 ,  G11C29/00

CPC classification number: G06F11/1072 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152

Abstract: Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

Abstract translation: 示例性实施例可以提供存储器件和存储器数据读取方法。 根据示例实施例的存储器件可以包括多位单元阵列，错误检测器，其可以从多位单元阵列中的存储器页读取第一数据页，并且可以检测第一数据页的错误位， 以及估计器，其可以识别存储错误位的多位单元，并且可以估计存储在所识别的多位单元中的数据在第二数据页的数据中。 因此，存储器件和存储器数据读取方法可以具有当读取存储在多位单元中的数据并且监视多位单元的状态而没有额外开销时减小误差的效果。

公开(公告)号：WO2008140171A1

公开(公告)日：2008-11-20

申请号：PCT/KR2008/000239

申请日：2008-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SONG, Seung-Hwan ,  KONG, Jun Jin ,  PARK, Sung Chung ,  CHAE, Dong Hyuk ,  LEE, Seung Jae ,  KANG, Dong Ku

IPC: G11C16/34

CPC classification number: G11C16/26 ,  G11C7/1006 ,  G11C11/5642

Abstract: Disclosed are an apparatus and a method for reading data. The method for reading data according to example embodiments includes comparing a threshold voltage of a memory cell with a first boundary voltage, comparing the threshold voltage with a second boundary voltage having a higher voltage level than that of the first boundary voltage, and determining data of the memory cell based on the threshold voltage, the first boundary voltage, and the second boundary voltage.

Abstract translation: 公开了一种用于读取数据的装置和方法。 根据示例实施例的用于读取数据的方法包括将存储器单元的阈值电压与第一边界电压进行比较，将阈值电压与具有比第一边界电压的电压电平更高的电压电平的第二边界电压进行比较，以及确定数据 所述存储单元基于所述阈值电压，所述第一边界电压和所述第二边界电压。

公开(公告)号：WO2008136562A1

公开(公告)日：2008-11-13

申请号：PCT/KR2007/005495

申请日：2007-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KONG, Jun Jin ,  SONG, Seung-Hwan ,  CHAE, Dong Hyuk ,  CHO, Kyoung Lae ,  LEE, Seung Jae ,  JO, Nam Phil ,  PARK, Sung Chung ,  KANG, Dong Ku

IPC: H03M13/29

CPC classification number: G06F11/1072

Abstract: An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.

Abstract translation: 应用于多电平单元（MLC）方法的存储器的错误控制代码（ECC）装置可以包括：产生旁路控制信号的旁路控制信号发生器; 以及ECC执行单元，其可以包括至少两个ECC解码块，基于旁路控制信号确定是否绕过所述至少两个ECC解码块的一部分，和/或执行ECC解码。 另外或作为替代，ECC执行单元可以包括至少两个ECC编码块，基于旁路控制信号确定是否绕过至少两个ECC编码块的一部分，和/或执行ECC编码。 还公开了应用于MLC方法的存储器的ECC方法和存储用于实现应用于MLC方法的存储器的EEC方法的程序的计算机可读记录介质。

公开(公告)号：WO2009116715A1

公开(公告)日：2009-09-24

申请号：PCT/KR2008/006190

申请日：2008-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YU, Donghun ,  CHO, Kyoung Lae ,  KANG, Dongku ,  CHAE, Dong Hyuk ,  KONG, Jun Jin

IPC: G11C16/34

CPC classification number: G11C16/26 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C29/00 ,  G11C2029/0411 ,  G11C2211/5621

Abstract: Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage intervals, a determination unit configured to determine data of a first bit layer based on the detected first threshold voltage intervals, and an error detection unit configured to detect an error bit of the data of the first bit layer. In this instance, the determination unit may determine data of a second bit layer using a second threshold voltage interval having a value of the first bit layer different from the detected error bit and being nearest to a threshold voltage of a multi-bit cell corresponding to the detected error bit.

Abstract translation: 公开了一种存储器件和存储器数据读取方法。 存储器件可以包括多位单元阵列，阈值电压检测单元，被配置为从多个阈值电压间隔中检测包括多位单元阵列的多位单元的阈值电压的第一阈值电压间隔， 单元，被配置为基于检测到的第一阈值电压间隔来确定第一位层的数据;以及错误检测单元，被配置为检测第一位层的数据的错误位。 在这种情况下，确定单元可以使用具有与检测到的错误位不同的第一位层的值的第二阈值电压间隔来确定第二位层的数据，并且最接近对应于多个位单元的阈值电压 检测到错误位。

公开(公告)号：WO2009102105A1

公开(公告)日：2009-08-20

申请号：PCT/KR2008/006185

申请日：2008-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SONG, Seung-Hwan ,  KONG, Jun Jin ,  KIM, Jae Hong ,  LEE, Young Hwan ,  CHAE, Dong Hyuk ,  KIM, Tae Hun ,  CHO, Kyoung Lae

IPC: G11C16/00

CPC classification number: G11C16/3418 ,  G11C7/04 ,  G11C11/5621 ,  G11C16/3427 ,  G11C16/349 ,  G11C29/00

Abstract: A memory device and a memory device heat treatment method are provided. The memory device may include: a non-volatile memory device; one or more heating devices configured to contact with the non-volatile memory device and heat the non-volatile memory device; and a controller configured to control an operation of the one or more heating devices based on operational information of the non-volatile memory device. Through this, it may be possible to improve an available period of the non-volatile memory device.

Abstract translation: 提供了一种存储器件和存储器件热处理方法。 存储器件可以包括：非易失性存储器件; 配置成与所述非易失性存储器件接触并加热所述非易失性存储器件的一个或多个加热器件; 以及控制器，被配置为基于所述非易失性存储器件的操作信息来控制所述一个或多个加热装置的操作。 由此，可以改善非易失性存储器件的可用周期。

公开(公告)号：WO2009051322A1

公开(公告)日：2009-04-23

申请号：PCT/KR2008/001998

申请日：2008-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SONG, Seung-Hwan ,  CHO, Kyoung Lae ,  EUN, Heeseok ,  CHAE, Dong Hyuk ,  KONG, Jun Jin ,  PARK, Sung Chung

IPC: G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3418 ,  G11C2211/5621

Abstract: Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may comprise: a multi-bit cell array that includes a first multi-bit cell and a second multi-bit cell; a programming unit for programming first data in the first multi-bit cell, and programming second data in the second multi-bit cell; and a verification unit for verifying whether the first data is programmed in the first multi-bit cell using a first verification voltage, and verifying whether the second data is programmed in the second multi-bit cell using a second verification voltage. The multi-bit programming apparatus may generate better threshold voltage distributions in a multi-bit cell memory.

Abstract translation: 提供了多位编程设备和/或方法。 多比特编程装置可以包括：包括第一多比特小区和第二多比特小区的多比特单元阵列; 编程单元，用于对第一多位单元中的第一数据进行编程，以及编程第二多位单元中的第二数据; 以及验证单元，用于使用第一验证电压来验证第一数据是否被编程在第一多位单元中，以及使用第二验证电压来验证第二数据是否被编程在第二多位单元中。 多比特编程装置可以在多比特单元存储器中产生更好的阈值电压分布。