公开(公告)号：WO2018118156A1

公开(公告)日：2018-06-28

申请号：PCT/US2017/050649

申请日：2017-09-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： MODI, Primit ,  RAMACHANDRA, Venkatesh ,  TANG, Tianyu ,  RAJENDRA, Srinivas

IPC: G11C29/02 ,  G11C7/22 ,  G11C7/10

CPC classification number: H03K3/017 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  H03K5/151 ,  H03K5/1565 ,  H03K7/08

Abstract: A complementary signal path may include an amplifier circuit (104) configured to receive a pair of complementary input signals (REnx, BREnx) and a data alignment circuit (106) configured to output a pair of complementary output signals (DQS, BDQS) in response to the pair of complementary input signals. A control circuit (102) may detect duty cycle distortion in the pair of complementary output signals and perform a duty cycle correction process to remove the distortion. To do so, the control circuit may search for target current amounts in response to the duty cycle distortion and inject a control current to intermediate signals (REAMP, BREAMP) in the amplifier circuit (104) at the target current amounts.

公开(公告)号：WO2019074677A1

公开(公告)日：2019-04-18

申请号：PCT/US2018/053090

申请日：2018-09-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： TANG, Tianyu ,  RAMACHANDRA, Venkatesh ,  RAJENDRA, Srinivas

IPC: G11C7/22

Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.

公开(公告)号：WO2018017189A1

公开(公告)日：2018-01-25

申请号：PCT/US2017/034938

申请日：2017-05-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： TANG, Tianyu ,  RAMACHANDRA, Venkatesh ,  RAJENDRA, Srinivas

IPC: H03K5/14 ,  H03K5/156 ,  G11C13/00

CPC classification number: H03K5/1565 ,  G11C7/222 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/32 ,  G11C2207/2254 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/77

Abstract: Systems and methods for generating periodic signals with reduced duty cycle variation are described. In some cases, a calibration procedure may be performed prior to a memory operation (e.g., prior to a read operation or a programming operation) in which a duty cycle correction circuit receives an input signal (e.g., an input clock signal), steps through various delay settings to determine a first delay setting corresponding with a signal high time for the input signal and a second delay setting corresponding with a signal low time for the input signal, generates a delayed version of the input signal corresponding with a mid-point delay setting between the first delay setting and the second delay setting, and generates a corrected signal using the delayed version of the input signal and the input signal.

Abstract translation: 描述了用于产生具有减小的占空比变化的周期性信号的系统和方法。 在一些情况下，可以在占空比校正电路接收输入信号（例如，输入时钟信号）的存储器操作之前（例如，在读取操作或编程操作之前）执行校准过程， 确定与输入信号的高信号时间对应的第一延迟设置和与输入信号的信号低时间对应的第二延迟设置的各种延迟设置生成与中点延迟对应的输入信号的延迟版本 设置在第一延迟设置和第二延迟设置之间，并且使用输入信号的延迟版本和输入信号产生校正信号。