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    METHODS OF MAKING LATERAL JUNCTION FIELD EFFECT TRANSISTORS USING SELECTIVE EPITAXIAL GROWTH
    1.
    发明申请
    METHODS OF MAKING LATERAL JUNCTION FIELD EFFECT TRANSISTORS USING SELECTIVE EPITAXIAL GROWTH 审中-公开
    使用选择性外延生长制造横截面场效应晶体管的方法

    公开(公告)号：WO2009129049A3

    公开(公告)日：2010-02-18

    申请号：PCT/US2009039107

    申请日：2009-04-01

    Applicant: SEMISOUTH LAB INC ,  MERRETT JOSEPH NEIL ,  SANKIN IGOR

    Inventor： MERRETT JOSEPH NEIL ,  SANKIN IGOR

    IPC: H01L21/336 ,  H01L21/20 ,  H01L29/78

    CPC classification number: H01L29/808 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66901

    Abstract: Methods of making a semiconductor device such as a lateral junction field effect transistor (JFET) are described. The methods are self-aligned and involve selective epitaxial growth using a regrowth mask material to form the gate or the source/drain regions of the device. The methods can eliminate the need for ion implantation. The device can be made from a wide band-gap semiconductor material such as SiC. The regrowth mask material can be TaC. The devices can be used in harsh environments including applications involving exposure to radiation and/or high temperatures.

    Abstract translation: 描述制造诸如横向结型场效应晶体管（JFET）的半导体器件的方法。 这些方法是自对准的，并且涉及使用再生长掩模材料选择性地外延生长以形成器件的栅极或源极/漏极区域。 该方法可以消除离子注入的需要。 该器件可以由诸如SiC的宽带隙半导体材料制成。 再生面膜材料可以是TaC。 该设备可用于恶劣环境，包括涉及辐射和/或高温的应用。

    SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING
    2.
    发明申请
    SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING 审中-公开
    具有增强导通的非穿通半导体通道的半导体器件及其制造方法

    公开(公告)号：WO2009137578A3

    公开(公告)日：2010-03-04

    申请号：PCT/US2009042983

    申请日：2009-05-06

    Applicant: SEMISOUTH LAB INC ,  SANKIN IGOR ,  SHERIDAN DAVID C ,  MERRETT JOSEPH NEIL

    Inventor： SANKIN IGOR ,  SHERIDAN DAVID C ,  MERRETT JOSEPH NEIL

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/8083 ,  H01L29/1058 ,  H01L29/1608 ,  H01L29/7392 ,  H01L29/7722

    Abstract: Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.

    Abstract translation: 描述了半导体器件，其中器件中的电流被限制在整流结（例如，p-n结或金属半导体结）之间。 该器件提供非穿通行为和增强的电流传导能力。 器件可以是功率半导体器件，例如结型场效应晶体管（VJFET），静态感应晶体管（SIT），结型场效应晶闸管或JFET限流器。 器件可以用碳化硅（SiC）等宽带隙半导体制造。 根据一些实施例，该器件可以是常闭SiC垂直结型场效应晶体管。 还描述了制造包括器件的器件和电路的方法。

    SEMICONDUCTOR DEVICE WITH SURGE CURRENT PROTECTION AND METHOD OF MAKING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE WITH SURGE CURRENT PROTECTION AND METHOD OF MAKING THE SAME 审中-公开
    具有浪涌电流保护的半导体器件及其制造方法

    公开(公告)号：WO2007130505A2

    公开(公告)日：2007-11-15

    申请号：PCT/US2007010712

    申请日：2007-05-01

    Applicant: SEMISOUTH LAB INC ,  SANKIN IGOR ,  MERRETT JOSEPH NEIL

    Inventor： SANKIN IGOR ,  MERRETT JOSEPH NEIL

    CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/868

    Abstract: A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions formed by plasma etching through the second epitaxial layer grown on the first epitaxial layer. Ohmic contacts are formed on p-type regions and on the backside of the n-type substrate. Schottky contacts are formed on the top surface of the n-type region. At normal operating conditions, the current in the device flows through the Schottky contacts. The device, however, is capable of withstanding extremely high current densities due to conductivity modulation caused by minority carrier injection from p-type regions.

    Abstract translation: 描述了具有浪涌电流保护的宽带隙半导体器件和制造该器件的方法。 该器件包括通过等离子体蚀刻形成的低掺杂n型区域，其通过在重掺杂n型衬底上生长的第一外延层和通过等离子体蚀刻形成的多个重掺杂p型区域形成，该区域通过在 第一外延层。 欧姆接触形成在p型区域和n型衬底的背面上。 在n型区域的顶表面上形成肖特基接触。 在正常工作条件下，器件中的电流流过肖特基触点。 然而，由于由p型区域的少数载流子注入引起的导电性调制，该器件能够承受极高的电流密度。

    LATERAL TRENCH FIELD-EFFECT TRANSISTORS IN WIDE BANDGAP SEMICONDUCTOR MATERIALS, METHODS OF MAKING, AND INTEGRATED CIRCUITS INCORPORATING THE TRANSISTORS
    6.
    发明申请
    LATERAL TRENCH FIELD-EFFECT TRANSISTORS IN WIDE BANDGAP SEMICONDUCTOR MATERIALS, METHODS OF MAKING, AND INTEGRATED CIRCUITS INCORPORATING THE TRANSISTORS 审中-公开
    宽带激光场效应晶体管在宽带半导体材料，制造方法和集成电路中并入晶体管

    公开(公告)号：WO2006060302A2

    公开(公告)日：2006-06-08

    申请号：PCT/US2005042871

    申请日：2005-11-30

    Applicant: SEMISOUTH LAB INC ,  SANKIN IGOR ,  CASADY JEFFREY B ,  MERRETT JOSPEH N

    Inventor： SANKIN IGOR ,  CASADY JEFFREY B ,  MERRETT JOSPEH N

    IPC: H01L31/111 ,  H01L21/332

    CPC classification number: H01L29/2003 ,  H01L27/098 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/808 ,  H01L29/8122

    Abstract: A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprise source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits comprising the devices are also described.

    Abstract translation: 描述了结型场效应晶体管。 晶体管由宽带隙半导体材料制成。 该器件包括源极，沟道，漂移和漏极半导体层以及p型注入或肖特基栅极区。 源极，沟道，漂移和漏极层可以外延生长。 到源极，栅极和漏极区域的欧姆接触可以形成在晶片的同一侧上。 器件可以具有取决于垂直沟道宽度的不同阈值电压，并且可以针对相同沟道掺杂的耗尽和增强的工作模式实现。 该器件可用于数字，模拟和单片微波集成电路。 还描述了制造包括这些器件的晶体管和集成电路的方法。

    SELF-ALIGNED SILICON CARBIDE SEMICONDUCTOR DEVICE
    7.
    发明申请
    SELF-ALIGNED SILICON CARBIDE SEMICONDUCTOR DEVICE 审中-公开
    自对准硅碳化硅半导体器件

    公开(公告)号：WO2005089303A3

    公开(公告)日：2007-04-05

    申请号：PCT/US2005008526

    申请日：2005-03-14

    Applicant: SEMISOUTH LAB INC ,  SANKIN IGOR ,  CASADY JANNA B ,  MERRETT JOSEPH N

    Inventor： SANKIN IGOR ,  CASADY JANNA B ,  MERRETT JOSEPH N

    IPC: H01L29/76 ,  H01L29/15 ,  H01L29/745 ,  H01L31/0312

    CPC classification number: H01L29/66068 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/45 ,  H01L29/66863 ,  H01L29/8128

    Abstract: A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n + -doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.

    Abstract translation: 描述了具有改善的电流稳定性的自对准碳化硅功率MESFET和制造该器件的方法。 该器件包括由栅极凹槽分隔开的升高的源极和漏极区域，由于甚至在低栅极偏置处降低的表面捕获效应，具有改善的电流稳定性。 可以使用自对准工艺来制造器件，其中在n掺杂的SiC沟道层上包括掺杂有n + n个掺杂的SiC层的衬底被蚀刻以限定凸起的源极和漏极区域（例如， 凸起的手指）使用金属蚀刻掩模。 然后将金属蚀刻掩模退火以形成源极和漏极欧姆接触。 然后生长或沉积单层或多层介电膜并进行各向异性蚀刻。 随后使用蒸发或其他各向异性沉积技术沉积肖特基接触层和最后的金属层，然后进行介电层或层的任意各向同性蚀刻。

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