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    HORIZONTALLY DEPLETED METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR
    1.
    发明申请
    HORIZONTALLY DEPLETED METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR 审中-公开
    水平金属半导体场效应晶体管

    公开(公告)号：WO2009036273A3

    公开(公告)日：2009-05-22

    申请号：PCT/US2008076169

    申请日：2008-09-12

    Applicant: UNIV ARIZONA STATE ,  ERVIN JOSEPH E ,  THORNTON TREVOR JOHN

    Inventor： ERVIN JOSEPH E ,  THORNTON TREVOR JOHN

    IPC: H01L21/338 ,  H01L29/10 ,  H01L29/423 ,  H01L29/812

    CPC classification number: H01L29/8124 ,  H01L29/1037 ,  H01L29/42316 ,  H01L29/4238 ,  H01L29/47 ,  H01L29/66848 ,  H01L29/7832 ,  H01L29/7855 ,  H01L29/8126 ,  H01L2029/7857

    Abstract: The present invention provides a horizontally depleted Metal Semiconductor Field Effect Transistor (MESFET). A drain region, a source region, and a channel region are formed in the device layer such that the drain region and the source region are spaced apart from one another and the channel region extends between the drain region and the source region. First and second gate contacts are formed in the device layer on either side of the channel region, and as such, the first and second gate contacts will also reside between opposing portions of the source and drain regions. With this configuration, voltages applied to the first and second gate contacts effectively control vertical depletion regions, which form on either side of the channel region.

    Abstract translation: 本发明提供了一种水平耗尽的金属半导体场效应晶体管（MESFET）。 漏极区域，源区域和沟道区域形成在器件层中，使得漏极区域和源极区域彼此间隔开，并且沟道区域在漏极区域和源极区域之间延伸。 第一和第二栅极触点形成在沟道区两侧的器件层中，因此第一和第二栅极触点也将位于源区和漏区的相对部分之间。 利用该配置，施加到第一和第二栅极触点的电压有效地控制在沟道区的任一侧上形成的垂直耗尽区。

    HORIZONTALLY DEPLETED METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR
    2.
    发明申请
    HORIZONTALLY DEPLETED METAL SEMICONDUCTOR FIELD EFFECT TRANSISTOR 审中-公开
    水平放置的金属半导体场效应晶体管

    公开(公告)号：WO2009036273A2

    公开(公告)日：2009-03-19

    申请号：PCT/US2008/076169

    申请日：2008-09-12

    Applicant: ARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY ,  ERVIN, Joseph, E. ,  THORNTON, Trevor, John

    Inventor： ERVIN, Joseph, E. ,  THORNTON, Trevor, John

    IPC: H01L21/338 ,  H01L29/10 ,  H01L29/423 ,  H01L29/812

    CPC classification number: H01L29/8124 ,  H01L29/1037 ,  H01L29/42316 ,  H01L29/4238 ,  H01L29/47 ,  H01L29/66848 ,  H01L29/7832 ,  H01L29/7855 ,  H01L29/8126 ,  H01L2029/7857

    Abstract: The present invention provides a horizontally depleted Metal Semiconductor Field Effect Transistor (MESFET). A drain region, a source region, and a channel region are formed in the device layer such that the drain region and the source region are spaced apart from one another and the channel region extends between the drain region and the source region. First and second gate contacts are formed in the device layer on either side of the channel region, and as such, the first and second gate contacts will also reside between opposing portions of the source and drain regions. With this configuration, voltages applied to the first and second gate contacts effectively control vertical depletion regions, which form on either side of the channel region.

    Abstract translation: 本发明提供水平耗尽的金属半导体场效应晶体管（MESFET）。 在器件层中形成漏极区域，源极区域和沟道区域，使得漏极区域和源极区域彼此间隔开，并且沟道区域在漏极区域和源极区域之间延伸。 第一和第二栅极接触形成在沟道区域的任一侧上的器件层中，因此，第一和第二栅极接触也将驻留在源极和漏极区域的相对部分之间。 利用这种配置，施加到第一和第二栅极接触的电压有效地控制垂直耗尽区，其在沟道区的任一侧上形成。

    NORMALLY-OFF JUNCTION FIELD-EFFECT TRANSISTORS AND COMPLEMENTARY CIRCUITS
    3.
    发明申请
    NORMALLY-OFF JUNCTION FIELD-EFFECT TRANSISTORS AND COMPLEMENTARY CIRCUITS 审中-公开
    正常关闭场效应晶体管和补充电路

    公开(公告)号：WO2015112472A1

    公开(公告)日：2015-07-30

    申请号：PCT/US2015/011966

    申请日：2015-01-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： HEKMATSHOARTABARI, Bahman ,  SHAHIDI, Ghavam G.

    IPC: H01L29/812 ,  H01L29/80 ,  H01L27/095

    CPC classification number: H01L29/8086 ,  H01L27/0617 ,  H01L27/098 ,  H01L29/1066 ,  H01L29/1604 ,  H01L29/802 ,  H01L29/8124 ,  H01L29/8126 ,  H01L29/868

    Abstract: A junction field-effect transistor (JFET) with a gate region that includes two separate subregions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices. According to an aspect of the present invention, there is a junction field effect transistor (JFET) that includes a channel region and a gate region. The gate region includes a first gate sub-region and a second gate sub-region. The first gate sub-region forms a junction with the channel region. The second gate sub-region forms a junction with the first gate sub-region. The channel region and the second gate sub-region include material of a first conductivity type. The first gate sub-region includes material of a second conductivity type different from the first conductivity type.

    Abstract translation: 具有栅极区域的结型场效应晶体管（JFET），栅极区域包括具有不同导电类型的材料的两个分开的子区域和/或当栅极结正向偏置时基本上抑制栅极电流的肖特基结以及互补电路 并入这种JFET器件。 根据本发明的一个方面，存在包括沟道区和栅极区的结型场效应晶体管（JFET）。 栅极区域包括第一栅极子区域和第二栅极子区域。 第一栅极子区域与沟道区域形成结。 第二栅极子区域与第一栅极子区域形成结。 沟道区域和第二栅极子区域包括第一导电类型的材料。 第一栅极子区域包括不同于第一导电类型的第二导电类型的材料。

    SPLIT-GATE FIELD EFFECT TRANSISTOR
    6.
    发明申请
    SPLIT-GATE FIELD EFFECT TRANSISTOR 审中-公开
    分离栅场效应晶体管

    公开(公告)号：WO1990007795A1

    公开(公告)日：1990-07-12

    申请号：PCT/US1989005861

    申请日：1989-12-29

    Applicant: REGENTS OF THE UNIVERSITY OF MINNESOTA

    Inventor： REGENTS OF THE UNIVERSITY OF MINNESOTA ,  SHUR, Michael

    IPC: H01L29/10

    CPC classification number: H01L29/42316 ,  H01L29/1029 ,  H01L29/7787 ,  H01L29/8124

    Abstract: A field effect transistor (28) having a gate voltage swing in the transistor channel (40) varying as a function of position between the drain (32) and the source (30). The gate voltage swing in the transistor channel (40) may be made to vary as a function of position by making the threshold voltage a function of position. Alternatively, a split-gate device (48) may be used by applying a voltage between the gates (70, 72). In both cases, the electric field near the source (50, 30) is raised to accelerate the electrons thereby decreasing electron transit time.

    NOVEL HIGH-SPEED INTEGRATED HETEROSTRUCTURE TRANSISTORS, PHOTODETECTORS, AND OPTOELECTRONIC CIRCUITS
    7.
    发明申请
    NOVEL HIGH-SPEED INTEGRATED HETEROSTRUCTURE TRANSISTORS, PHOTODETECTORS, AND OPTOELECTRONIC CIRCUITS 审中-公开
    新型高速集成结构晶体管，光电转换器和光电电路

    公开(公告)号：WO1989012323A1

    公开(公告)日：1989-12-14

    申请号：PCT/US1989002401

    申请日：1989-06-01

    Applicant: REGENTS OF THE UNIVERSITY OF MINNESOTA

    Inventor： REGENTS OF THE UNIVERSITY OF MINNESOTA ,  SHUR, Michael ,  SIMMONS, John, G.

    IPC: H01L31/10

    CPC classification number: H01L29/737 ,  H01L27/1443 ,  H01L29/1075 ,  H01L29/7783 ,  H01L29/8124 ,  H01L31/112

    Abstract: A high-speed heterostructure planar integrated circuit includes a planar photodetector (30) together with a transistor (either a Modulation-Doped-0 Field Effect Transistor 50 or a lateral p-n-p bipolar transistor 120). The planar photodetector (30) includes a bottom confinement layer (12) of a wide bandgap material, a heavily doped first conductivity-type buried layer (14) over the bottom confinement layer, a relatively undoped higher index of refraction layer (16) overlying the buried layer (14), a top confinement layer (18) of wider bandgap material which has a lower index of refraction, a first vertical contact region (32) of first conductivity type which extends downward to make electrical contact with the buried layer, and a second contact region (34) of second conductivity type spaced laterally from the first contact region (32) and extending through the top confinement layer (18) and a portion of the undoped layer (16). As a result of the difference in refractive indices of undoped versus doped regions and in wide gap versus narrow gap material, light directed into one end of the photodetector (30) is confined both laterally and vertically to the undoped layer (16) where it is absorbed. Charge separation occurs with first conductivity carriers being collected at the first contact region (32) and the buried layer (14), and second conductivity carriers being collected at the second contact region.

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