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公开(公告)号:WO2022257063A1
公开(公告)日:2022-12-15
申请号:PCT/CN2021/099318
申请日:2021-06-10
发明人: ZHANG, Zhong , WANG, Di , ZHOU, Wenxi
IPC分类号: H01L27/11582
摘要: In certain aspects, a three-dimensional (3D) memory device includes a plurality of channel structures in a first region, a staircase structure in a second region, and a word line extending in the first region and the second region. The first region and the second region are arranged along a first direction. The word line is discontinuous in the first direction between the first region and the second region.
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2.
公开(公告)号:WO2022133995A1
公开(公告)日:2022-06-30
申请号:PCT/CN2020/139361
申请日:2020-12-25
发明人: ZHANG, Zhong
IPC分类号: H01L27/11551 , H01L27/11578
摘要: A 3D memory device includes a memory stack having a memory block. The memory block includes a first memory array structure, a staircase structure, a second memory array structure in a first lateral direction, and a plurality of fingers in a second lateral. The staircase structure includes a staircase zone and a bridge structure adjacent to the staircase zone in the second lateral direction. The 3D memory device also includes a source-select-gate (SSG) cut structure extending in a SSG of the memory stack and between adjacent ones of the plurality of fingers of the memory block. The SSG cut structure is between a first finger and a second finger, the first finger includes a string. The staircase zone includes a staircase conductively connected to memory cells in the string in each of the first memory array structure and the second memory array structure through the bridge structure.
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公开(公告)号:WO2022087772A1
公开(公告)日:2022-05-05
申请号:PCT/CN2020/123597
申请日:2020-10-26
发明人: KONG, Cuicui , ZHANG, Zhong , WU, Linchun , ZHANG, Kun , ZHOU, Wenxi
IPC分类号: H01L27/11582 , H01L27/1157
摘要: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a semiconductor layer, a supporting structure, a spacer structure, and a contact structure. The memory stack includes interleaved conductive layers and dielectric layers and includes a staircase region in a plan view. The semiconductor layer is in contact with the memory stack. The supporting structure overlaps the staircase region of the memory stack and is coplanar with the semiconductor layer. The supporting structure includes a material other than a material of the semiconductor layer. The spacer structure is outside the memory stack and is coplanar with the supporting structure and the semiconductor layer. The contact structure extends vertically and is surrounded by the spacer structure.
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公开(公告)号:WO2022021269A1
公开(公告)日:2022-02-03
申请号:PCT/CN2020/106068
申请日:2020-07-31
发明人: WU, Linchun , ZHANG, Kun , ZHANG, Zhong , ZHOU, Wenxi , XIA, Zhiliang
IPC分类号: H01L27/115
摘要: Methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a semiconductor device (200) includes an insulating layer (202), a conductive layer (208) over the insulating layer (202), and a spacer structure (220) in the conductive layer (208) and in contact with the insulating layer (202). The semiconductor device (200) also includes a first contact structure (216) in the spacer structure (220) and extending vertically through the insulating layer (202). The first contact structure (216) includes a first contact portion (216-1) and a second contact portion (216-2) in contact with each other. An upper surface of the second contact portion (216-2) is coplanar with an upper surface of the conductive layer (208).
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公开(公告)号:WO2021237403A1
公开(公告)日:2021-12-02
申请号:PCT/CN2020/092081
申请日:2020-05-25
发明人: SUN, Zhongwang , ZHANG, Zhong , LIU, Lei , ZHOU, Wenxi , XIA, Zhiliang
IPC分类号: H01L27/1157 , H01L27/11582
摘要: Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.
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公开(公告)号:WO2021208268A1
公开(公告)日:2021-10-21
申请号:PCT/CN2020/100567
申请日:2020-07-07
发明人: ZHANG, Kun , ZHANG, Zhong , LIU, Lei , ZHOU, Wenxi , XIA, Zhiliang
IPC分类号: H01L27/11
摘要: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer above and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts are distributed below and in contact with the source line mesh.
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公开(公告)号:WO2021237629A1
公开(公告)日:2021-12-02
申请号:PCT/CN2020/093067
申请日:2020-05-29
发明人: ZHANG, Zhong
IPC分类号: H01L27/1157 , H01L27/11582
摘要: A semiconductor device has a stack formed of word line layers and insulating layers that are alternatingly arranged over a substrate. A first connection region is arranged between first array regions in the stack, and a first separation structure positioned along first sides of the first connection region and the first array regions. The first separation structure extends through the stack into the substrate. A second separation structure is positioned along opposing second sides of the first connection region and the first array regions. The second separation structure includes array separation structures positioned along the second sides of the first array regions and a connection separation structure positioned along the second side of the first connection region. The connection separating structure is arranged between and aligned with the array separation structures, and further extends through the stack into the substrate.
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8.
公开(公告)号:WO2021189190A1
公开(公告)日:2021-09-30
申请号:PCT/CN2020/080670
申请日:2020-03-23
发明人: ZHANG, Zhong , SUN, Zhongwang , ZHOU, Wenxi , XIA, Zhiliang
IPC分类号: H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L27/11519 , H01L27/11551 , H01L27/11565 , H01L27/11578
摘要: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes a plurality of stairs. At least one stair in the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.
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公开(公告)号:WO2021179273A1
公开(公告)日:2021-09-16
申请号:PCT/CN2020/079087
申请日:2020-03-13
发明人: SUN, Zhongwang , ZHANG, Zhong , ZHOU, Wenxi , LIU, Lei , XIA, Zhiliang
IPC分类号: H01L21/768
摘要: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.
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公开(公告)号:WO2021127980A1
公开(公告)日:2021-07-01
申请号:PCT/CN2019/127921
申请日:2019-12-24
发明人: ZHANG, Zhong , SUN, Zhongwang , ZHOU, Wenxi , XIA, Zhiliang , ZHANG, Zhi
IPC分类号: H01L27/11524 , G11C8/14 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要: A semiconductor device is provided that can include a stack formed of word line layers and insulating layers that are alternatingly stacked over a substrate. A first staircase of a first block can be formed in the stack and extend between first array regions of the first block. A second staircase of a second block can be formed in the stack and extend between second array regions of the second block. The semiconductor device further can have a connection region that is formed in the stack between the first staircase and second staircase.
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