THREE-DIMENSIONAL MEMORY DEVICE HAVING SOURCE-SELECT-GATE CUT STRUCTURES AND METHODS FOR FORMING SAME

    公开(公告)号:WO2022133995A1

    公开(公告)日:2022-06-30

    申请号:PCT/CN2020/139361

    申请日:2020-12-25

    发明人: ZHANG, Zhong

    IPC分类号: H01L27/11551 H01L27/11578

    摘要: A 3D memory device includes a memory stack having a memory block. The memory block includes a first memory array structure, a staircase structure, a second memory array structure in a first lateral direction, and a plurality of fingers in a second lateral. The staircase structure includes a staircase zone and a bridge structure adjacent to the staircase zone in the second lateral direction. The 3D memory device also includes a source-select-gate (SSG) cut structure extending in a SSG of the memory stack and between adjacent ones of the plurality of fingers of the memory block. The SSG cut structure is between a first finger and a second finger, the first finger includes a string. The staircase zone includes a staircase conductively connected to memory cells in the string in each of the first memory array structure and the second memory array structure through the bridge structure.

    METHODS FOR FORMING CONTACT STRUCTURES AND SEMICONDUCTOR DEVICES THEREOF

    公开(公告)号:WO2022021269A1

    公开(公告)日:2022-02-03

    申请号:PCT/CN2020/106068

    申请日:2020-07-31

    IPC分类号: H01L27/115

    摘要: Methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a semiconductor device (200) includes an insulating layer (202), a conductive layer (208) over the insulating layer (202), and a spacer structure (220) in the conductive layer (208) and in contact with the insulating layer (202). The semiconductor device (200) also includes a first contact structure (216) in the spacer structure (220) and extending vertically through the insulating layer (202). The first contact structure (216) includes a first contact portion (216-1) and a second contact portion (216-2) in contact with each other. An upper surface of the second contact portion (216-2) is coplanar with an upper surface of the conductive layer (208).

    MEMORY DEVICE AND METHOD FOR FORMING THE SAME

    公开(公告)号:WO2021237403A1

    公开(公告)日:2021-12-02

    申请号:PCT/CN2020/092081

    申请日:2020-05-25

    IPC分类号: H01L27/1157 H01L27/11582

    摘要: Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

    THREE-DIMENSIONAL MEMORY DEVICE WITH BACKSIDE INTERCONNECT STRUCTURES

    公开(公告)号:WO2021208268A1

    公开(公告)日:2021-10-21

    申请号:PCT/CN2020/100567

    申请日:2020-07-07

    IPC分类号: H01L27/11

    摘要: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer above and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts are distributed below and in contact with the source line mesh.

    THREE-DIMENSIONAL NAND MEMORY DEVICE AND FORMING METHOD THEREOF

    公开(公告)号:WO2021237629A1

    公开(公告)日:2021-12-02

    申请号:PCT/CN2020/093067

    申请日:2020-05-29

    发明人: ZHANG, Zhong

    IPC分类号: H01L27/1157 H01L27/11582

    摘要: A semiconductor device has a stack formed of word line layers and insulating layers that are alternatingly arranged over a substrate. A first connection region is arranged between first array regions in the stack, and a first separation structure positioned along first sides of the first connection region and the first array regions. The first separation structure extends through the stack into the substrate. A second separation structure is positioned along opposing second sides of the first connection region and the first array regions. The second separation structure includes array separation structures positioned along the second sides of the first array regions and a connection separation structure positioned along the second side of the first connection region. The connection separating structure is arranged between and aligned with the array separation structures, and further extends through the stack into the substrate.

    CONTACT STRUCTURES FOR THREE-DIMENSIONAL MEMORY

    公开(公告)号:WO2021179273A1

    公开(公告)日:2021-09-16

    申请号:PCT/CN2020/079087

    申请日:2020-03-13

    IPC分类号: H01L21/768

    摘要: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.