公开(公告)号：WO2023027786A1

公开(公告)日：2023-03-02

申请号：PCT/US2022/028631

申请日：2022-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： SHIMOMURA, Kenichi

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11575

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures vertically extending through the alternating stack. An insulating liner overlies stepped surfaces of the alternating stack in a staircase region. A plurality of discrete dielectric plates can be formed over the insulating liner. In one embodiment, the plurality of discrete dielectric plates can function as etch stop structures for formation of contact via structures that contact underlying portions of the electrically conductive layers. In another embodiment, the plurality of discrete dielectric plates may be replaced with a metallic material that forms extensions of the electrically conductive layers, and can be employed as etch stop structures during formation of contact via structures.

公开(公告)号：WO2022231662A1

公开(公告)日：2022-11-03

申请号：PCT/US2021/065564

申请日：2021-12-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： SAID, Ramy Nashed Bassely ,  MAKALA, Raghuveer S. ,  KANAKAMEDALA, Senaka ,  SHARANGPANI, Rahul

IPC: H01L27/11587 ,  H01L27/1159 ,  H01L27/11597 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/792

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings extending through the alternating stack, and memory opening fill structures located in the memory openings and containing a respective vertical semiconductor channel and a respective memory film. Each of the electrically conductive layers includes a tubular metallic liner in contact with a respective outer sidewall segment of a respective one of the memory opening fill structures, an electrically conductive barrier layer contacting the respective tubular metallic liner and two of the insulating layers, and a metallic fill material layer contacting the electrically conductive barrier layer, and not contacting the tubular metallic liner or any of the insulating layers. The memory opening fill structures are formed after performing a halogen outgassing anneal through the memory openings to reduce or eliminate the halogen outgassing damage in the layers of the memory film.

公开(公告)号：WO2022203703A1

公开(公告)日：2022-09-29

申请号：PCT/US2021/035016

申请日：2021-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： MATSUNO, Koichi ,  HIGASHITANI, Masaaki ,  ALSMEIER, Johann

IPC: H01L27/11548 ,  H01L27/11575 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/8234

Abstract: A semiconductor structure includes a semiconductor device, bit lines electrically connected to the semiconductor device, air gaps located between the bit lines, a capping-level material layer, a via-level dielectric material layer located between the bit lines and the capping-level material layer, and conductive via structures extending through the via-level dielectric material layer and contacting a top surface of a respective one of the bit lines. The capping-level material layer contains cavity-containing openings exposing the air gaps. The capping-level material layer contains protruding portions that extend into peripheral regions of the cavity-containing openings.

公开(公告)号：WO2022052029A1

公开(公告)日：2022-03-17

申请号：PCT/CN2020/114724

申请日：2020-09-11

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD

Inventor： LIU, Wei ,  HUANG, Shiqi ,  CHEN, Liang

IPC: H01L23/552 ,  H01L27/11519 ,  H01L27/11524

Abstract: A semiconductor device (100) includes a first die. The first die includes a semiconductor substrate with transistors formed on a first side of the semiconductor substrate. Further, the first die includes a connection structure (170) extending through the semiconductor substrate and conductively connecting a first conductive layer disposed on the first side of the semiconductor substrate with a second conductive layer disposed on a second side of the semiconductor substrate that is opposite to the first side of the semiconductor substrate. Further, the first die includes a shielding structure (160) disposed in the semiconductor substrate and between the connection structure (170) and at least a transistor. The shielding structure (160) includes a third conductive layer and can alleviate coupling between the connection structure (170) and the transistor.

公开(公告)号：WO2022047331A1

公开(公告)日：2022-03-03

申请号：PCT/US2021/048281

申请日：2021-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： CLAMPITT, Darwin A. ,  LYONSMITH, Shawn D. ,  KING, Matthew J. ,  CLAMPITT, Lisa M. ,  HOPKINS, John ,  TITUS, Kevin Y. ,  CHARY, Indra V. ,  BARCLAY, Martin Jared ,  CHANDOLU, Anilkumar ,  NATARAJAN, Pavithra ,  LINDSAY, Roger W.

IPC: H01L27/11565 ,  H01L27/11519 ,  H01L27/11575 ,  H01L27/11548 ,  H01L21/8234

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：WO2021247181A1

公开(公告)日：2021-12-09

申请号：PCT/US2021/030850

申请日：2021-05-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： GREENLEE, Jordan, D. ,  HOPKINS, John, D.

IPC: H01L27/11568 ,  H01L27/11582 ,  H01L27/11575 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/0847

Abstract: Some embodiments include an integrated assembly having a source structure. The source structure includes, in ascending order, a first conductively-doped semiconductor material, one or more first insulative layers, a second conductively-doped semiconductor material, one or more second insulative layers, and a third conductively-doped semiconductor material. The source structure includes blocks extending through the second conductively-doped semiconductor material. Conductive levels are over the source structure. Channel material extends vertically along the conductive levels, and extends into the source structure to be in direct contact with the second conductively-doped semiconductor material. One or more memory cell materials are between the channel material and the conductive levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：WO2021243703A1

公开(公告)日：2021-12-09

申请号：PCT/CN2020/094658

申请日：2020-06-05

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： WANG, Di ,  ZHOU, Wenxi ,  XIA, Zhiliang

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  G11C8/14 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/11565

Abstract: 3D memory devices (100, 200) having staircase structures (102, 202-1, 202-2) and methods for forming the same are provided. The 3D memory device (100, 200) includes a memory array structure (104-1, 104-2, 204) and a staircase structure (102, 202-1, 202-2) in an intermediate of the memory array structure (104-1, 104-2, 204). The staircase structure (102, 202-1, 202-2) includes a plurality of stairs (114, 214, 314, 414) extending along the lateral direction, and a bridge structure (108, 208, 308, 408) in contact with a first memory array structure (104-1) and a second memory array structure (104-2). The plurality of stairs (114, 214, 314, 414) includes a stair (114, 214, 314, 414) above one or more dielectric pairs. The stair (114, 214, 314, 414) includes a conductor portion (320, 420) on a top surface of the stair (114, 214, 314, 414) and in contact with and electrically connected to the bridge structure (108, 208, 308, 408), and is electrically connected to at least one of the first memory array structure (104-1) and a second memory array structure (104-2) of the memory array structure (104-1, 104-2, 204) through the bridge structure (108, 208, 308, 408). Along a second lateral direction, a width of the conductor portion (320, 420) is unchanged.

公开(公告)号：WO2021024071A1

公开(公告)日：2021-02-11

申请号：PCT/IB2020/056864

申请日：2020-07-22

Applicant: 株式会社半導体エネルギー研究所

Inventor： 山崎舜平 ,  木村肇 ,  松嵜隆徳 ,  大貫達也 ,  岡本佑樹 ,  魚地秀貴 ,  岡本悟

IPC: H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/11509 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1156 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792 ,  H01L29/786 ,  G11C16/04

Abstract: 信頼性の高い記憶装置を提供する。 第１方向に延在する第１導電体の側面に、第１導電体側から見て、第１絶縁体と、第１半導体と、第２絶縁体と、第２半導体と、第３絶縁体とを順に設ける。第１導電体に、第１絶縁体、第１半導体、第２絶縁体、第２半導体、および第３絶縁体を介して第２導電体と重なる第１領域と、第１絶縁体、第１半導体、第２絶縁体、第２半導体、および第３絶縁体を介して第３導電体と重なる第２領域を設ける。第２領域において、第１絶縁体と第１半導体の間に第４導電体を設ける。

公开(公告)号：WO2018161836A1

公开(公告)日：2018-09-13

申请号：PCT/CN2018/077719

申请日：2018-03-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： LU, Zhenyu ,  SHI, Wenguang ,  WU, Guanping ,  WAN, Xianjin ,  CHEN, Baoyou

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11578

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes a substrate including a peripheral circuit, and an alternating layer stack disposed on the substrate. The alternating layer stack includes a first region including an alternating dielectric stack, a second region including an alternating conductor/dielectric stack, and a third region including staircase structures on edges of the alternating conductor/dielectric layer stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region or the third region, multiple channel structures and multiple slit structures each extending vertically through the alternating conductor/dielectric stack, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with the peripheral circuit.

公开(公告)号：WO2023033880A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/028223

申请日：2022-05-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： HINOUE, Tatsuya

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11597 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11587 ,  H01L27/11575 ,  H01L27/11548

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. The sacrificial material layers include a stack of word-line-level sacrificial material layers and at least one drain-select-level sacrificial material layer. Drain-select-level openings are formed through the at least one drain-select-level sacrificial material layer, which is replaced with at least one drain-select-level electrically conductive layer. Memory openings are formed by vertically extending the drain-select-level openings through the word-line-level sacrificial material layers. Memory opening fill structures are formed within the memory openings. The word-line-level sacrificial material layers are replaced with word-line-level electrically conductive layers.