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    SYSTEMS, METHODS, AND APPARATUS FOR FREQUENCY RESET OF A MEMORY
    1.
    发明申请
    SYSTEMS, METHODS, AND APPARATUS FOR FREQUENCY RESET OF A MEMORY 审中-公开
    用于存储器频率重置的系统，方法和装置

    公开(公告)号：WO2017023408A1

    公开(公告)日：2017-02-09

    申请号：PCT/US2016/035520

    申请日：2016-06-02

    Applicant: QUALCOMM INCORPORATED

    Inventor： JOSE, Edwin ,  WANG, Tao

    IPC: G06F13/16

    CPC classification number: G06F11/1471 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0679 ,  G06F13/1668 ,  G06F2201/805 ,  G06F2201/84 ,  G06F2201/85

    Abstract: Some aspects of the disclosure include a self-refresh entry sequence for a memory, such as a DRAM, that may be used to avoid a frequency mismatch between a system processor and a system memory. The self-refresh entry sequence may signal the memory to reset the frequency set point state and default to the power-up state upon a self-refresh process exit. In another aspect, a new mode register may be used to indicate that the frequency set point needs to be reset after the next self-refresh entry command. In this aspect, the processor will execute a mode register write command followed by a self-refresh entry in response to the occurrence of a crash event. Then, the memory will reset to the default frequency set point by the end of self-refresh entry execution.

    Abstract translation: 本公开的一些方面包括用于诸如DRAM的存储器的自刷新入口序列，其可以用于避免系统处理器和系统存储器之间的频率不匹配。 自刷新入口序列可能会在存储器中发信号通知复位频率设定点状态，并在自刷新过程退出时默认为上电状态。 另一方面，可以使用新的模式寄存器来指示频率设定点需要在下一个自刷新输入命令之后复位。 在这方面，处理器将执行模式寄存器写入命令，随后响应于碰撞事件的发生而进行自刷新条目。 然后，在自刷新输入执行结束时，存储器将重置为默认频率设定点。

    TECHNIQUES FOR ERROR HANDLING IN PARALLEL SPLITTING OF STORAGE COMMANDS
    2.
    发明申请
    TECHNIQUES FOR ERROR HANDLING IN PARALLEL SPLITTING OF STORAGE COMMANDS 审中-公开
    并行分裂存储命令中的错误处理技巧

    公开(公告)号：WO2016054469A2

    公开(公告)日：2016-04-07

    申请号：PCT/US2015053640

    申请日：2015-10-02

    Applicant: NETAPP INC

    Inventor： MU PAUL YUEDONG ,  NGAN PAUL ,  SUNDARARAJAN MANOJ

    IPC: G06F11/14

    CPC classification number: H04L1/08 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/067 ,  G06F3/0689 ,  G06F11/07 ,  G06F11/2069 ,  G06F11/2094 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2201/85

    Abstract: Various embodiments are generally directed to techniques for handling errors affecting the at least partially parallel performance of data access commands between nodes of a storage cluster system. An apparatus may include a processor component of a first node, an access component to perform a command received from a client device via a network to alter client device data stored in a first storage device coupled to the first node, a replication component to transmit a replica of the command to a second node via the network to enable performance of the replica by the second node at least partially in parallel, an error component to retry transmission of the replica based on a failure indicated by the second node and a status component to select a status indication to transmit to the client device based on the indication of failure and results of retrial of transmission of the replica.

    Abstract translation: 各种实施例通常针对用于处理影响存储集群系统的节点之间的数据访问命令的至少部分并行执行的错误的技术。 一种设备可以包括第一节点的处理器组件，访问组件以执行经由网络从客户端设备接收的命令以改变存储在耦合到第一节点的第一存储设备中的客户端设备数据，复制组件发送 通过网络将命令复制到第二节点以使第二节点至少部分地并行地执行复制品，基于由第二节点指示的故障和状态组件重新发送复制品的错误组件到 基于失败的指示和副本的传输的重试结果，选择状态指示以发送到客户端设备。

    SYSTEMS AND METHODS FOR RECOVERING FROM UNCORRECTED DRAM BIT ERRORS
    3.
    发明申请
    SYSTEMS AND METHODS FOR RECOVERING FROM UNCORRECTED DRAM BIT ERRORS 审中-公开
    从不确定的DRAM位错误中恢复的系统和方法

    公开(公告)号：WO2015160835A1

    公开(公告)日：2015-10-22

    申请号：PCT/US2015/025798

    申请日：2015-04-14

    Applicant: QUALCOMM INCORPORATED

    Inventor： CHUN, Dexter Tamio ,  LI, Yanru ,  KIM, Jung Pill ,  SRIRAMAGIRI, Deepti Vijayalakshmi

    IPC: G06F11/10

    CPC classification number: G06F11/2017 ,  G06F3/0688 ,  G06F11/0772 ,  G06F11/08 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1417 ,  G06F2201/85 ,  G06F2212/1032 ,  G06F2212/7201 ,  G11C29/00 ,  G11C29/08 ,  G11C29/52 ,  G11C29/70

    Abstract: Systems, methods, and computer programs are disclosed for recovering from dynamic random access memory (DRAM) defects. One method comprises determining that an uncorrected bit error has occurred for a physical codeword address associated with a dynamic random access memory (DRAM) device coupled to a system on chip (SoC). A kernel page associated with a DRAM page comprising the physical codeword address is identified as a bad page. Recovery from the uncorrected bit error is provided by rebooting a system comprising the SoC and the DRAM device. In response to the rebooting, the identified kernel page is excluded from being allocated for DRAM operation.

    Abstract translation: 公开了用于从动态随机存取存储器（DRAM）缺陷中恢复的系统，方法和计算机程序。 一种方法包括确定与耦合到片上系统（SoC）的动态随机存取存储器（DRAM）设备相关联的物理码字地址已经发生未校正的位错误。 与包括物理码字地址的DRAM页面相关联的内核页面被识别为坏页面。 通过重新启动包括SoC和DRAM设备的系统来提供从未校正的位错误的恢复。 响应于重新启动，识别的内核页面被排除在为DRAM操作分配之前。

    IN-BAND RECOVERY MECHANISM FOR I/O MODULES IN A DATA STORAGE SYSTEM
    5.
    发明申请
    IN-BAND RECOVERY MECHANISM FOR I/O MODULES IN A DATA STORAGE SYSTEM 审中-公开
    数据存储系统中I / O模块的带内恢复机制

    公开(公告)号：WO2015112564A1

    公开(公告)日：2015-07-30

    申请号：PCT/US2015/012197

    申请日：2015-01-21

    Applicant: NETAPP, INC.

    Inventor： SAXENA, Mayank ,  MCGEE, Melvin

    IPC: G06F13/14

    CPC classification number: G06F11/201 ,  G06F11/0727 ,  G06F11/0793 ,  G06F11/2012 ,  G06F11/2089 ,  G06F13/426 ,  G06F2201/805 ,  G06F2201/85 ,  H04L45/22 ,  H04L47/35

    Abstract: Technology is disclosed for recovering I/O modules in a storage system using in-band alternate control path (ACP) architecture ("the technology"). The technology enables a storage server to transmit control commands, e.g., for recovering an I/O module, to the I/O module over a data path that is typically used to transmit data commands. The control commands are typically transmitted using ACP that is separate from the data path. By enabling transmission of control commands over the data path, the technology eliminates the need for separate medium for ACP, at least in part, to transmit the control commands. The technology can be implemented in a pure in-band ACP mode, which supports recovering an I/O module of a storage shelf in which at least one I/O module is responsive, and/or in a mixed in-band ACP mode, which supports recovery of I/O modules of a storage shelf in which all I/O modules are non responsive.

    Abstract translation: 公开了用于使用带内替代控制路径（ACP）架构（“该技术”）在存储系统中恢复I / O模块的技术。 该技术使得存储服务器能够通过通常用于发送数据命令的数据路径向I / O模块发送例如用于恢复I / O模块的控制命令。 控制命令通常使用与数据路径分离的ACP传输。 通过使数据路径上的控制命令能够传输，该技术消除了对于ACP的单独介质的需要，至少部分地传送控制命令。 该技术可以以纯带内ACP模式实现，其支持恢复其中至少一个I / O模块响应的存储架的I / O模块和/或混合带内ACP模式， 其支持恢复所有I / O模块不响应的存储架的I / O模块。

    FELDBUSREDUNDANZ FÜR NICHT REDUNDANTES FELDGERÄT
    6.
    发明申请
    FELDBUSREDUNDANZ FÜR NICHT REDUNDANTES FELDGERÄT 审中-公开
    FELDBUSREDUNDANZ不适用于冗余现场设备

    公开(公告)号：WO2015043903A1

    公开(公告)日：2015-04-02

    申请号：PCT/EP2014/068788

    申请日：2014-09-04

    Applicant: SIEMENS AKTIENGESELLSCHAFT

    Inventor： BOTH, Thomas ,  REUPKE, Jürgen

    IPC: G05B19/042 ,  H04L12/40 ,  H04L29/08

    CPC classification number: H04L12/40045 ,  G06F11/2007 ,  G06F2201/85 ,  H04L67/12 ,  H04L69/40

    Abstract: Eine Eingabeeinrichtung zur Abtastung eines externen Prozesses durch ein entferntes Rechnersystem umfasst einen Schnittstellenbaustein zur Bereitstellung einer Information in Abhängigkeit von einem externen Signal und eine Vermittlungseinrichtung zur Verbindung des Schnittstellenbausteins mit einem ersten und einem davon unabhängigen zweiten Netzwerk, die jeweils zur Verbindung mit dem Rechnersystem eingerichtet sind. Dabei ist die Vermittlungseinrichtung dazu eingerichtet, die bereitgestellte Information vom Schnittstellenbaustein entgegen zu nehmen und alternativ über das erste oder das zweite Netzwerk zu übertragen.

    Abstract translation: 用于通过远程计算机系统感测外部过程的输入装置包括用于响应于外部信号和用于连接具有第一和它们的独立的第二网络接口模块的开关装置提供信息的接口模块，每个适于连接到计算机系统 ， 该开关被配置为接受由所述接口模块计数器所提供的信息，并通过第一或第二网络可替代地发送。

    PARTITIONABLE DATA BUS
    8.
    发明申请
    PARTITIONABLE DATA BUS 审中-公开
    可分区数据总线

    公开(公告)号：WO2015006946A1

    公开(公告)日：2015-01-22

    申请号：PCT/CN2013/079572

    申请日：2013-07-18

    Applicant: ADVANCED MICRO DEVICES, INC. ,  LOH, Gabriel H. ,  XU, Yi ,  O’CONNOR, James M.

    Inventor： LOH, Gabriel H. ,  XU, Yi ,  O’CONNOR, James M.

    IPC: G06F9/45

    CPC classification number: G06F11/2007 ,  G06F11/0745 ,  G06F11/0763 ,  G06F2201/85

    Abstract: A method and a system are provided for partitioning a system data bus. The method can include partitioning off a portion of a system data bus that includes one or more faulty bits to form a partitioned data bus. Further, the method includes transferring data over the partitioned data bus to compensate for data loss due to the one or more faulty bits in the system data bus.

    Abstract translation: 提供了一种分区系统数据总线的方法和系统。 该方法可以包括分离包括一个或多个故障位的系统数据总线的一部分以形成分区数据总线。 此外，该方法包括在分区数据总线上传送数据以补偿由于系统数据总线中的一个或多个故障位导致的数据丢失。

    ACTIVE HOST AND BACKUP HOST IN A HOST ARRANGEMENT FOR COMMUNICATING WITH A TERMINAL CONNECTED TO AN IP NETWORK
    9.
    发明申请
    ACTIVE HOST AND BACKUP HOST IN A HOST ARRANGEMENT FOR COMMUNICATING WITH A TERMINAL CONNECTED TO AN IP NETWORK 审中-公开
    主机主机和主机主机连接到与IP网络连接的终端

    公开(公告)号：WO2014098681A1

    公开(公告)日：2014-06-26

    申请号：PCT/SE2012/051465

    申请日：2012-12-20

    Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)

    Inventor： WOLLBRAND, Per ,  AMMERVIK, Clarence ,  TÖRNKVIST, Åke

    IPC: H04L29/08 ,  H04L29/12

    CPC classification number: G06F11/2007 ,  G06F11/2028 ,  G06F11/2033 ,  G06F11/2041 ,  G06F2201/815 ,  G06F2201/85 ,  H04L61/103 ,  H04L67/1034 ,  H04L69/40

    Abstract: A method in a host arrangement for communicating with a terminal connected to an IP communication network. The arrangement comprises at least two hosts, one operating as active host and the remaining at least one host operating as backup host(s). The arrangement is connected to the IP communication network by means of a switch, wherein each host of the arrangement is connected to the switch by means of an individual link, the active host being associated with an IP and a MAC address. The method comprises detecting (110) a link failure between the active host and the switch, or a malfunction of the active host; and determining (120) a backup host to takeover. The method comprises associating (130) the IP and the MAC address of the active host to the determined backup host to take over; and triggering (140) a MAC learning process in the switch.

    Abstract translation: 一种用于与连接到IP通信网络的终端通信的主机装置中的方法。 该装置包括至少两个主机，一个作为活动主机运行，剩余的至少一个主机作为备份主机运行。 该布置通过交换机连接到IP通信网络，其中该装置的每个主机通过单独的链路连接到交换机，活动主机与IP和MAC地址相关联。 该方法包括检测（110）活动主机与交换机之间的链路故障或活动主机的故障; 以及确定（120）备份主机以接管。 该方法包括将活动主机的IP和MAC地址与确定的备份主机相关联（130），以接管; 并触发（140）交换机中的MAC学习过程。

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