Abstract:
A decoder according to one embodiment of the invention includes a set of lines, a resonator circuit, a set of input leads for receiving input signals, and a set of switches for coupling some of the lines within the set of lines to the resonator circuit in response to the input signals while the other lines within the set of lines are at a first binary voltage. The lines are coupled to a set of pointer circuits. The pointer circuits perform logic functions on the signals on the lines when the resonating signal is at a second binary voltage opposite the first binary voltage to thereby decode the input signals. Because the lines are driven high and low by a resonator circuit, the decoder circuit power consumption is less than it would be if the lines were pulled up and down by a set of pullup and pulldown transistors.
Abstract:
A crystal oscillator is started in a high power mode for a certain period of time to ensure starting oscillation with average grade crystals, then once the certain time period is over the oscillator switches into a low power mode and sustains oscillation with energy pulses triggered by and synchronized with the oscillator output frequency. These energy pulses may be generated on the positive, negative or both positive and negative edges of the clock output waveform.
Abstract:
Circuits having corresponding methods and computer-readable media comprise: an amplifier; a crystal port configured to be electrically coupled to a crystal, wherein a first terminal of the crystal port is electrically coupled to an input of the amplifier, and wherein a second terminal of the crystal port is electrically coupled to an output of the amplifier; a first capacitor, wherein a first terminal of the first capacitor is electrically coupled to ground; a second capacitor, wherein a first terminal of the second capacitor is electrically coupled to ground; a first switch configured to selectively electrically couple the input of the amplifier to a second terminal of the first capacitor; and a second switch configured to selectively electrically couple the output of the amplifier to a second terminal of the second capacitor.
Abstract:
An oscillator assembly includes an oscillator circuit that is configured to generate a frequency signal. A temperature compensation circuit is in communication with the oscillator circuit and adapted to adjust the frequency signal in response to changes in temperature. The oscillator and temperature compensation circuits are located within an oven. A heater and a temperature sensor in communication with the heater are also both located in the oven. The temperature sensor is adapted to directly control the heater in response to changes in temperature. In one embodiment, the oscillator components are mounted to a ball grid array substrate which, in turn, is mounted on a printed circuit board. In this embodiment, a resonator overlies the ball grid array substrate and a lid covers and defines an oven and enclosure for the resonator and the ball grid array substrate. The oscillator and temperature compensation circuit are defined on the ball grid array substrate.
Abstract:
A method and system for fast wakeup of a high-Q oscillator that includes a resonating element, preferably a crystal resonator, and an amplifier. The method comprises connecting the resonating element to a fast wakeup, low-Q oscillator, inputting a plurality of pulses generator by the low-Q oscillator into the resonating element, and simutaneously disconnecting the resonating element from the low-Q oscillator while connecting the resonating element to the amplifier, thereby obtaining substantially uniform steady state oscillations in the high-Q oscillator. The system includes in addition to high-Q and low-Q oscillator elements a mechanism for counting the pulses and for performing the simultaneous disconnection and connection mentioned above.
Abstract:
There is described an electronic device including an electronic circuit (1, 8) for delivering an output signal (CKS) and a programmable non volatile memory (30) coupled to the electronic circuit to allow storage of a binary word (EED[7:0]) representative of at least one adjustable feature (C1, C2) of the electronic circuit (1, 8),this electronic device including at least first and second supply terminals (PAD_VDD, PAD_VSS), to which first and second supply voltages are applied (V DD , V 55 ) and at least one output terminal (PAD_OUT) at which the output signal from the electronic circuit is delivered. Means are provided for switching the output terminal into a so-called high impedance state so as to allow the introduction, in serial form, via this output terminal, of data bits intended, in particular, to be stored in the non volatile memory of the device. This device is applied, in particular, for adjusting the features of an oscillator circuit. Figure 3