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公开(公告)号：WO2019220123A1
公开(公告)日：2019-11-21
申请号：PCT/GB2019/051346
申请日：2019-05-16
发明人： DE OLIVEIRA, Joao
IPC分类号： H03K3/012 , H03K19/094 , H03K19/0944
摘要： An AND gate comprises:a first input;a second input;an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output. Also disclosed is a clock divider stage for receiving a first clock signal oscillating at a first frequency and a second clock signal, the second clock signal being an inversion of the first clock signal, and generating a first output clock signal oscillating at half of the first frequency.
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公开(公告)号：WO2018055371A1
公开(公告)日：2018-03-29
申请号：PCT/GB2017/052806
申请日：2017-09-20
IPC分类号： H01L29/423 , H01L29/49 , H01L29/786
摘要： A transistor is disclosed, comprising: a layer of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion; a conductive first terminal covering and in electrical contact with said first portion of the layer of semiconductor material; a conductive second terminal covering and in electrical contact with said second portion of the layer of semiconductor material; a conductive gate terminal comprising a first overlapping portion covering at least part of the first terminal, and a channel portion covering the third portion of the layer of semiconductor material; and a layer of a first dielectric material, having a first dielectric constant, arranged between the first overlapping portion and the first terminal, and between the channel portion of the gate terminal and the third portion of the layer of semiconductor material. The transistor further comprises a layer of a second dielectric material having a second dielectric constant, the second dielectric constant being lower than the first dielectric constant, the layer of second dielectric material being arranged between at least part of the first overlapping portion and the first terminal, whereby at least part of the first overlapping portion of the gate terminal is separated from the first terminal by the layer of first dielectric material and the layer of second dielectric material.
摘要翻译： 公开了一种晶体管，包括：半导体材料层，其包括第一部分，第二部分和将所述第一部分连接至所述第二部分的第三部分，并且在所述第一部分与所述第二部分之间提供半导电沟道， 和第二部分; 导电的第一端子，覆盖所述半导体材料层的所述第一部分并与所述第一部分电接触; 导电的第二端子，覆盖并与所述半导体材料层的所述第二部分电接触; 导电栅极端子，包括覆盖所述第一端子的至少一部分的第一重叠部分和覆盖所述半导体材料层的第三部分的沟道部分; 以及布置在第一重叠部分和第一端子之间以及栅极端子的沟道部分和半导体材料层的第三部分之间的具有第一介电常数的第一介电材料层。 所述晶体管还包括具有第二介电常数的第二介电材料层，所述第二介电常数低于所述第一介电常数，所述第二介电材料层布置在所述第一重叠部分的至少一部分与所述第一端子 由此，栅极端子的第一重叠部分的至少一部分通过第一介电材料层和第二介电材料层与第一端子分离。
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3.发明申请
公开(公告)号：WO2017141013A1
公开(公告)日：2017-08-24
申请号：PCT/GB2017/050330
申请日：2017-02-09
CPC分类号： H01L24/75 , H01L24/81 , H01L24/97 , H01L2224/1329 , H01L2224/133 , H01L2224/75601 , H01L2224/75611 , H01L2224/7565 , H01L2224/75651 , H01L2224/7598 , H01L2224/81192 , H01L2224/95115 , H01L2224/97 , H01L2924/00014
摘要： A method of manufacturing a plurality of electronic circuits is disclosed. Each electronic circuit comprises a respective first portion, comprising a respective group of contact pads, and a respective integrated circuit, IC, comprising a respective group of terminals and mounted on the respective group of contact pads with each terminal in electrical contact with a respective contact pad. The method comprises: providing a first structure comprising the plurality of first portions; providing a second structure comprising the plurality of ICs and a common support arranged to support the plurality of ICs; transferring said ICs from the common support onto a first roller; transferring said ICs from the first roller onto a second roller; and transferring said ICs from the second roller onto the first structure such that each group of terminals is mounted on a respective group of contact pads.
摘要翻译： 公开了一种制造多个电子电路的方法。 每个电子电路包括相应的第一部分和相应的集成电路IC，所述相应的第一部分包括相应的一组接触垫，所述相应的集成电路IC包括相应的端子组并且安装在相应的接触垫组上，每个端子与相应的接触部电接触 垫。 该方法包括：提供包括多个第一部分的第一结构; 提供包括所述多个IC的第二结构和布置成支持所述多个IC的公共支撑; 将所述IC从所述公共支撑件转移到第一辊上; 将所述IC从所述第一辊转移到第二辊上; 以及将所述IC从所述第二辊转移到所述第一结构上，使得每组端子安装在相应的一组接触垫上。
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公开(公告)号：WO2021079131A1
公开(公告)日：2021-04-29
申请号：PCT/GB2020/052672
申请日：2020-10-22
发明人： PRICE, Richard , COBB, Brian
摘要： An electronic circuit comprises a first resistor (1) and a second resistor (2). The first resistor comprises: a first sheet (10) of resistive material; and a first pair (11, 12) of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness (LI) of the first sheet. The second resistor comprises: a second sheet (20) of resistive material; and a second pair (21, 22) of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path (L2) in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet.
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公开(公告)号：WO2021032978A1
公开(公告)日：2021-02-25
申请号：PCT/GB2020/051987
申请日：2020-08-19
IPC分类号： H01L27/12
摘要： A method of manufacturing an electronic circuit (or circuit module) (100) is disclosed. The electronic circuit comprises a transistor (1) and a resistor (2), the transistor comprising a source terminal (11), a drain terminal (12), a gate terminal (13), and a first body (10) of material providing a controllable semi-conductive channel between the source and drain terminals, and the resistor comprises a first resistor terminal (21), a second resistor terminal (22), and a second body (20) of material providing a resistive current path between the first resistor terminal and the second resistor terminal. The method comprises: forming the first body (10); and forming the second body (20), wherein the first body comprises a first quantity (100) of a metal oxide and the second body comprises a second quantity (200) of said metal oxide. Corresponding electronic circuits are disclosed.
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公开(公告)号：WO2019150100A1
公开(公告)日：2019-08-08
申请号：PCT/GB2019/050250
申请日：2019-01-30
发明人： PRICE, Richard David , DAVIES, Neil , WHITE, Scott , VAN DEN HEEVER, Thomas Stanley , WILLIAMSON, Kenneth David , GREEN, Nathaniel James
IPC分类号： H01L21/67 , H01L21/677
摘要： The invention relates to a system for manufacturing a plurality of integrated circuits, IC, mounted on a common support, the system comprising: an input station configured (adapted, arranged) to receive at least one common support; an output station configured (adapted, arranged) to receive at least one common support having a plurality of integrated circuits formed thereon; a plurality of processing modules each module being operable (configured, arranged, adapted) to perform at least one of the processing steps (e.g. deposition, patterning, etching) for forming an integrated circuit on the common support; a transfer means operable (configured, arranged, adapted) to transfer the at least one common support from the input station to the output station and to one or more of the processing modules therebetween; control means (e.g. a control system, or at least one controller, control unit, or control module) operable to direct the at least one common support from the input station to the output station through one or more of the plurality of processing modules according to at least one processing protocol comprising a selected one of a plurality of changeable pre-programmed protocols; the control means being operable to direct the movement of a common support from the input station to the output station and through one or more of the processing modules independently of any other common support. The invention also relates to a method for manufacturing a plurality of integrated circuits, IC, mounted on a common support.
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公开(公告)号：WO2019116020A1
公开(公告)日：2019-06-20
申请号：PCT/GB2018/053588
申请日：2018-12-11
发明人： ALKHALIL, Feras , PRICE, Richard , COBB, Brian
IPC分类号： H01L29/872 , H01L21/329 , H01L29/417 , H01L29/47 , H01L51/05 , H01L29/06 , H01L29/20 , H01L29/16 , H01L29/24 , H01L29/22
摘要： A Schottky diode comprises:a first electrode;a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface,wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.
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公开(公告)号：WO2018178657A1
公开(公告)日：2018-10-04
申请号：PCT/GB2018/050805
申请日：2018-03-27
IPC分类号： H01L27/06 , H01L21/822
摘要： A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal. Methods of manufacturing such structures are also disclosed.
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公开(公告)号：WO2015079243A1
公开(公告)日：2015-06-04
申请号：PCT/GB2014/053525
申请日：2014-11-28
发明人： DE OLIVEIRA, Joao
CPC分类号： H01Q1/2225 , G06K7/10158 , G06K19/07783 , G08B13/2417 , H01Q1/2216 , H01Q1/38 , H01Q1/44 , H01Q7/00 , H04B5/0081
摘要： An antenna comprises: a first terminal; a second terminal; and a winding, having an inductance, comprising a plurality of turns and connected between the first and second terminals such that a change in magnetic flux linking the winding generates a corresponding voltage between said terminals. The winding comprises a conductive element connected to the first and second terminals and extending around said turns from the first terminal to the second terminal and having a thickness not exceeding Χμm along a length of the conductive element from the first to the second terminal and a width not exceeding Χμm along said length, where X is less than or equal to 10, whereby said conductive element is substantially non-visible to a naked human eye.
摘要翻译： 天线包括：第一终端; 第二个终端 以及具有电感的绕组，包括多个匝并连接在第一和第二端子之间，使得连接绕组的磁通量的变化在所述端子之间产生相应的电压。 所述绕组包括连接到所述第一端子和所述第二端子的导电元件，并且围绕所述匝从所述第一端子延伸到所述第二端子，并且沿着所述导电元件的从所述第一端子到所述第二端子的长度具有不超过Xλ的厚度， 沿着所述长度不超过X 1，其中X小于或等于10，由此所述导电元件对于裸眼睛基本上不可见。
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公开(公告)号：WO2013121195A1
公开(公告)日：2013-08-22
申请号：PCT/GB2013/050337
申请日：2013-02-13
CPC分类号： H01L29/66477 , G03F7/2022 , H01L27/1266 , H01L29/66757 , H01L29/66765 , H01L29/66969
摘要： A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below the substrate, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.
摘要翻译： 一种制造电子器件的方法，包括第一端子（例如源极端子），第二端子（例如漏极端子），连接第一和第二端子的半导体沟道和可以施加电位的栅极端子以控制 通道的电导率。 该方法包括使用掩模从衬底上方首先曝光光致抗蚀剂，并从衬底下方第二曝光，其中在第二曝光中，第一和第二端子屏蔽光刻胶的一部分不被曝光。 中间步骤降低了在第一次曝光中暴露的光致抗蚀剂的溶解度。 在被掩模遮蔽的位置处的光致抗蚀剂中形成窗口，但是暴露于下方的辐射。 半导体材料，电介质材料和导体材料沉积在窗口内，分别形成半导体沟道，栅极电介质和栅极端子。
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