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    PREVENTING OVER-PROGRAMMING OF ReRAM-BASED MEMORY CELLS
    1.
    发明申请
    PREVENTING OVER-PROGRAMMING OF ReRAM-BASED MEMORY CELLS 审中-公开
    预防基于ReRAM的存储器单元的过度编程

    公开(公告)号：WO2018064414A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2017/054174

    申请日：2017-09-28

    Applicant: MICROSEMI SOC CORP.

    Inventor： HECHT, Volker

    IPC: G11C13/00

    CPC classification number: G11C13/0059 ,  G11C13/0023 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0066 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/79

    Abstract: A method for preventing over-programming of resistive random access (ReRAM) based memory cells in a ReRAM memory array includes applying a programming voltage in a programming circuit path including a ReRAM memory cell to be programmed, sensing programming current drawn by the ReRAM cell while the programming voltage is applied across the memory cell, and decreasing the programming current as a function of a rise in programming current.

    Abstract translation: 用于防止ReRAM存储器阵列中的基于电阻随机存取（ReRAM）的存储器单元的过度编程的方法包括在包括待编程的ReRAM存储器单元的编程电路路径中施加编程电压，感测 在将编程电压施加到存储器单元两端时由ReRAM单元汲取的编程电流，以及作为编程电流上升的函数来减小编程电流。

    ON-CHIP PROBE CIRCUIT FOR DETECTING FAULTS IN AN FPGA
    2.
    发明申请
    ON-CHIP PROBE CIRCUIT FOR DETECTING FAULTS IN AN FPGA 审中-公开
    用于检测FPGA中的故障的片上探测电路

    公开(公告)号：WO2014008234A1

    公开(公告)日：2014-01-09

    申请号：PCT/US2013/049029

    申请日：2013-07-02

    Applicant: MICROSEMI SOC CORP.

    Inventor： GREENE, Jonathan ,  KANNEMACHER, Dirk ,  HECHT, Volker ,  SPEERS, Theodore

    IPC: G01R31/3185 ,  G01R31/317

    CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/318519

    Abstract: An integrated programmable logic circuit having a read/write probe includes a plurality of programmable logic circuits having internal circuit nodes and a plurality of flip flops, each having an asynchronous data input line, an asynchronous load line, and a data output connected to an internal circuit node, a probe-data line, an address circuit for selecting one of the internal circuit nodes, a read-probe enable line for selectively coupling the selected one of the internal circuit nodes to the probe-data line, a data input path to the asynchronous data input line of each flip flop, a write- probe data input path to the asynchronous data input line of each flip flop, a write- probe enable line, and selection circuitry, responsive to the address circuit and the write-probe enable line, to couple one of the data input path and the write-probe data input path to the asynchronous data input of a selected flip flop.

    Abstract translation: 具有读/写探头的集成可编程逻辑电路包括具有内部电路节点和多个触发器的多个可编程逻辑电路，每个具有异步数据输入线，异步负载线和连接到内部的数据输出 电路节点，探针数据线，用于选择内部电路节点之一的地址电路，用于选择性地将所选择的一个内部电路节点耦合到探测数据线的读取探测使能线，数据输入路径 每个触发器的异步数据输入线，每个触发器的异步数据输入线的写入探针数据输入路径，写入探针使能线和选择电路，响应于地址电路和写入探针使能 将数据输入路径和写入探针数据输入路径之一耦合到所选择的触发器的异步数据输入。

    RESISTIVE RANDOM ACCESS MEMORY CELL WITH THREE TRANSISTORS AND TWO RESISTIVE MEMORY ELEMENTS
    5.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY CELL WITH THREE TRANSISTORS AND TWO RESISTIVE MEMORY ELEMENTS 审中-公开
    具有三个晶体管和两个电阻性存储元件的电阻式随机存取存储器单元

    公开(公告)号：WO2018063446A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2017/031795

    申请日：2017-05-09

    Applicant: MICROSEMI SOC CORP.

    Inventor： MC COLLUM, John, L. ,  HECHT, Volker

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C2013/0042 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436

    Abstract: A ReRAM cell array has rows and columns and includes first and second complementary bit lines for each row, a first, second and third word lines for each column and a source bit line for each row. A ReRAM cell at each row and column includes a first resistive memory element, its first end connected to the first complementary bit line of its row, a p-channel transistor, its source connected to a second end of the first resistive memory element, its drain connected to a switch node, its gate connected to the first word line of its column, a second resistive memory element, its first end connected to the second complementary bit line of its row, an n-channel transistor, its source connected to a second end of the second resistive memory element, its drain connected to the switch node, its gate connected to the second word line of its column, and a programming transistor having a drain connected to the switch node, a source connected to the source bit line of its row and a gate connected to the third word line of its column.

    Abstract translation: ReRAM单元阵列具有行和列，并且包括每行的第一和第二互补位线，每列的第一，第二和第三字线以及每行的源位线。 每行和每列的ReRAM单元包括第一电阻式存储器元件，其第一端连接到其行的第一互补位线，p沟道晶体管，其源极连接到第一电阻式存储器元件的第二端， 漏极连接到开关节点，其栅极连接到其列的第一字线，第二电阻式存储器元件，其第一端连接到其行的第二互补位线，n沟道晶体管，其源极连接到 第二电阻式存储器元件的第二端，其漏极连接到开关节点，其栅极连接到其列的第二字线，以及编程晶体管，其漏极连接到开关节点，源极连接到源位线 的行和连接到其列的第三个字线的门。

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