公开(公告)号：WO2022209029A1

公开(公告)日：2022-10-06

申请号：PCT/JP2021/045431

申请日：2021-12-03

申请人： MITSUBISHI ELECTRIC CORPORATION ,  MITSUBISHI ELECTRIC R&D CENTRE EUROPE B.V.

发明人： PICHON, Pierre-Yves ,  BRANDELERO, Julio ,  OUHAB, Merouane ,  DEGRENNE, Nicolas

IPC分类号： H01L21/607 ,  H01L23/49 ,  B23K20/00 ,  B23K20/004 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/056 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48458 ,  H01L2224/4851 ,  H01L2224/78315 ,  H01L2224/78901 ,  H01L2224/85205 ,  H01L2224/8593 ,  H01L2224/85947 ,  H01L2224/85948 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85

摘要： The invention relates to producing a semiconductor chip-metal wire bond, by performing the steps of bonding a wire having a metal body to the semiconductor chip so as to connect the wire to the semiconductor chip, the bond metal having a polycrystalline microstructure, and deforming a bonding region of the metal body in contact with to the semiconductor chip, the deformed bonding region being characterized by a relative cross section area change given by (AA), where Af is a final cross section area and A0 is an initial cross section area, the deformation involving an increase of a dislocation density in the microstructure of at least a portion of the bonding region.

公开(公告)号：WO2022271250A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/022615

申请日：2022-03-30

申请人： INTEL CORPORATION

发明人： ALEKSOV, Aleksandar ,  EID, Feras ,  SWAN, Johanna M. ,  ELSHERBINI, Adel A. ,  LIFF, Shawna M.

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L2224/05014 ,  H01L2224/06051 ,  H01L2224/06132 ,  H01L2224/2512 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/25 ,  H01L25/0652

摘要： Embodiments disclosed herein include semiconductor dies with hybrid bonding layers and multi-die modules that are coupled together by hybrid bonding layers. In an embodiment, a semiconductor die comprises a die substrate, a pad layer over the die substrate, where the pad layer comprises first pads with a first dimension and a first pitch and second pads with a second dimension and a second pitch. In an embodiment, the semiconductor die further comprises a hybrid bonding layer over the pad layer. In an embodiment, the hybrid bonding layer comprises a dielectric layer, and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads comprise a third dimension and a third pitch.