公开(公告)号：WO2013142713A1

公开(公告)日：2013-09-26

申请号：PCT/US2013/033344

申请日：2013-03-21

Applicant: MICRON TECHNOLOGY, INC. ,  SANDHU, Gurtej, S. ,  KINNEY, Wayne, I.

Inventor： SANDHU, Gurtej, S. ,  KINNEY, Wayne, I.

IPC: G11C11/15 ,  H01L27/115 ,  H01L21/8247

CPC classification number: H01L43/08 ,  G11C11/15 ,  G11C11/161 ,  H01F10/1936 ,  H01F10/3286 ,  H01F10/329 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: Memory cells including cell cores having free regions are disclosed. The free regions exhibit a strain that affects a magnetization orientation within the cell core. A stressor structure may exert a stress upon at least a portion of the cell core to effect the strain state of the free region. Also disclosed are semiconductor device structures and systems including such memory cells as well as methods for forming such memory cells.

Abstract translation: 公开了包括具有自由区域的单元芯的存储单元。 自由区域表现出影响细胞核心内的磁化取向的应变。 应力结构可能对细胞芯的至少一部分施加应力以实现自由区的应变状态。 还公开了包括这种存储单元的半导体器件结构和系统以及用于形成这种存储单元的方法。

公开(公告)号：WO2013015935A2

公开(公告)日：2013-01-31

申请号：PCT/US2012/044484

申请日：2012-06-27

Applicant: MICRON TECHNOLOGY, INC. ,  SANDHU, Gurtej, S.

Inventor： SANDHU, Gurtej, S.

IPC: H01L27/02

CPC classification number: H01L21/768 ,  H01L23/525 ,  H01L23/53276 ,  H01L29/0665 ,  H01L29/0676 ,  H01L29/1606 ,  H01L29/66022 ,  H01L29/66742 ,  H01L29/7788 ,  H01L29/78642 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming graphene-containing switches. A bottom electrode may be formed over a base, and a first electrically conductive structure may be formed to extend upwardly from the bottom electrode. Dielectric material may be formed along a sidewall of the first electrically conductive structure, while leaving a portion of the bottom electrode exposed. A graphene structure may be formed to be electrically coupled with the exposed portion of the bottom electrode. A second electrically conductive structure may be formed on an opposing side of the graphene structure from the first electrically conductive structure. A top electrode may be formed over the graphene structure and electrically coupled with the second electrically conductive structure. The first and second electrically conductive structures may be configured to provide an electric field across the graphene structure.

Abstract translation: 一些实施方案包括形成含石墨烯开关的方法。 底部电极可以形成在基底上，并且第一导电结构可以形成为从底部电极向上延伸。 电介质材料可以沿着第一导电结构的侧壁形成，同时使底部电极的一部分暴露。 石墨烯结构可以形成为与底部电极的暴露部分电耦合。 第二导电结构可以形成在石墨烯结构的与第一导电结构相反的一侧上。 顶部电极可以形成在石墨烯结构上并且与第二导电结构电耦合。 第一和第二导电结构可以被配置成提供穿过石墨烯结构的电场。

公开(公告)号：WO2012158347A2

公开(公告)日：2012-11-22

申请号：PCT/US2012/036083

申请日：2012-05-02

Applicant: MICRON TECHNOLOGY, INC. ,  LIU, Jun ,  SANDHU, Gurtej S.

Inventor： LIU, Jun ,  SANDHU, Gurtej S.

CPC classification number: G11C11/16 ,  G11C11/161 ,  H01L29/66984 ,  H01L43/02 ,  H01L43/08

Abstract: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise an annular STT stack including a nonmagnetic material between a first ferromagnetic material and a second ferromagnetic material and a soft magnetic material surrounding at least a portion of the annular STT stack.

Abstract translation: 本文描述了旋转转矩传递（STT）存储单元结构和方法。 一个或多个STT存储器单元结构包括在第一铁磁材料和第二铁磁材料之间包括非磁性材料的环形STT堆叠和围绕环形STT堆叠的至少一部分的软磁材料。

公开(公告)号：WO2012036728A2

公开(公告)日：2012-03-22

申请号：PCT/US2011001573

申请日：2011-09-13

Applicant: MICRON TECHNOLOGY INC ,  KRAMER STEPHEN J ,  SANDHU GURTEJ S

Inventor： KRAMER STEPHEN J ,  SANDHU GURTEJ S

IPC: G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08

Abstract: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material and a multiferroic material in contact with the ferromagnetic storage material, wherein the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are located between a first electrode and a second electrode.

Abstract translation: 自旋转矩传输（STT）存储器单元结构和方法在本文中描述。 一个或多个STT存储器单元结构包括位于铁磁存储材料和与反铁磁材料接触的钉扎铁磁材料和与铁磁存储材料接触的多铁性材料之间的钉扎铁磁材料之间的隧穿势垒材料，其中反铁磁材料，铁磁存储材料 并且钉扎铁磁材料位于第一电极和第二电极之间。

公开(公告)号：WO2011093995A2

公开(公告)日：2011-08-04

申请号：PCT/US2011/000134

申请日：2011-01-25

Applicant: MICRON TECHNOLOGY, INC. ,  SMYTHE III, John, A. ,  SANDHU, Gurtej, S.

Inventor： SMYTHE III, John, A. ,  SANDHU, Gurtej, S.

IPC: H01L27/105 ,  H01L21/8247

CPC classification number: H01L45/165 ,  G11C13/0007 ,  G11C2213/56 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1641 ,  H01L45/1683

Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.

Abstract translation: 本公开包括GCIB处理的电阻性装置，利用GCIB处理的电阻性装置（例如，作为开关，存储器单元）的装置以及用于形成经GCIB处理的电阻装置的方法。 形成GCIB处理的电阻性器件的一种方法包括形成下电极，并在下电极上形成氧化物材料。 将氧化物材料暴露于气体簇离子束（GCIB），直到氧化物材料的第一部分的电阻相对于氧化物材料的第二部分的电阻发生变化。 在第一部分上形成上电极。

公开(公告)号：WO2011028581A3

公开(公告)日：2011-03-10

申请号：PCT/US2010/046672

申请日：2010-08-25

Applicant: MICRON TECHNOLOGY, INC. ,  RAMASWAMY, Nirmal ,  SANDHU, Gurtej S.

Inventor： RAMASWAMY, Nirmal ,  SANDHU, Gurtej S.

IPC: H01L27/115 ,  H01L21/8247

Abstract: Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described.

公开(公告)号：WO2010110987A2

公开(公告)日：2010-09-30

申请号：PCT/US2010/025495

申请日：2010-02-26

Applicant: MICRON TECHNLOLOGY, INC. ,  SILLS, Scott ,  SANDHU, Gurtej, S.

Inventor： SILLS, Scott ,  SANDHU, Gurtej, S.

IPC: H01L21/027

CPC classification number: G03F7/0035

Abstract: A method of forming a pattern on a substrate includes forming spaced first features over a substrate. The spaced first features have opposing lateral sidewalls. Material is formed onto the opposing lateral sidewalls of the spaced first features. That portion of such material which is received against each of the opposing lateral sidewalls is of different composition from composition of each of the opposing lateral sidewalls. At least one of such portion of the material and the spaced first features is densified to move the at least one laterally away from the other of the at least one to form a void space between each of the opposing lateral sidewalls and such portion of the material.

Abstract translation: 在衬底上形成图案的方法包括在衬底上形成间隔开的第一特征。 间隔开的第一特征具有相对的侧向侧壁。 材料形成在间隔开的第一特征的相对的侧向侧壁上。 抵靠每个相对的侧向侧壁的这种材料的该部分的组成与每个相对的侧向侧壁的组成不同。 材料的这种部分和间隔开的第一特征中的至少一个被致密化以使所述至少一个横向移动远离另一个至少一个，以在每个相对的侧向侧壁和材料的这一部分之间形成空隙空间 。

公开(公告)号：WO2010096094A1

公开(公告)日：2010-08-26

申请号：PCT/US2009/057017

申请日：2009-09-15

Applicant: MICRON TECHNOLOGY, INC. ,  LIU, Jun ,  SANDHU, Gurtej, S.

Inventor： LIU, Jun ,  SANDHU, Gurtej, S.

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/02225 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

Abstract: A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state -changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.

Abstract translation: 一种方法包括在具有含金属的导电互连的集成电路上形成电绝缘体材料，并激活衬底的半导体材料中的掺杂剂以提供掺杂区域。 掺杂区域提供相反导电类型的结。 在激活掺杂剂之后，衬底被结合到绝缘体材料上，并且至少部分衬底在与绝缘体材料接合的情况下被去除。 在去除之后，形成具有字线，存取二极管，含有硫族化物相变材料的状态可变存储元件和全部电连接的位线的存储单元，该存储二极管包含接合点作为pn结 。 存储器件包括绝缘体材料上的粘附材料并将字线连接到绝缘体材料。

公开(公告)号：WO2010059451A3

公开(公告)日：2010-08-26

申请号：PCT/US2009063761

申请日：2009-11-09

Applicant: MICRON TECHNOLOGY INC ,  SRINIVASAN BHASKAR ,  SANDHU GURTEJ S

Inventor： SRINIVASAN BHASKAR ,  SANDHU GURTEJ S

IPC: H01L29/861

CPC classification number: H01L29/88 ,  H01L21/3205 ,  H01L27/1021 ,  Y10S438/957

Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select device may comprise, for example, a metal insulator insulator metal (MIIM) device. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.

Abstract translation: 公开了包括用作具有低介电常数的高带隙材料的开放体积的器件。 开放体积可以在选择器件中提供更加非线性的非对称I-V曲线和增强的整流行为。 选择装置可以包括例如金属绝缘体绝缘金属（MIIM）装置。 可以使用各种方法来形成包括这种选择装置的选择装置和存储器系统。 存储器设备和电子系统包括这种选择设备。

公开(公告)号：WO2007127496A8

公开(公告)日：2010-08-19

申请号：PCT/US2007011524

申请日：2007-05-14

Applicant: MICRON TECHNOLOGY INC ,  SANDHU GURTEJ S

Inventor： SANDHU GURTEJ S

IPC: B82B3/00 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L21/3081 ,  G03F7/0002 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  Y10T428/24058 ,  Y10T428/2995

Abstract: A pattern having exceptionally small features is formed on a partially fabricated integrated circuit (102) during integrated circuit fabrication. The pattern comprises features (162), (164) formed by self-organizing material, such as diblock copolymers. The organization of the copolymers is directed by spacers (152) which have been formed by a pitch multiplication process in which the spacers (152) are formed at the sides of sacrificial mandrels (142), which are later removed to leave the spaced-apart, free-standing spacers (152). Diblock copolymers, composed of two immiscible block species, are deposited over and in the space between the spacers (152). The copolymers are made to self-organize, with each block species aggregating with other block species of the same type.

Abstract translation: 在集成电路制造期间，在部分制造的集成电路（102）上形成具有特别小特征的图案。 图案包括由自组织材料形成的特征（162），（164），例如二嵌段共聚物。 共聚物的组织由间隔物（152）引导，间隔物（152）已经通过间距倍增过程形成，其中间隔物（152）形成在牺牲心轴（142）的侧面，后者被去除以离开间隔开 ，独立式间隔件（152）。 由两个不混溶的嵌段物质组成的二嵌段共聚物沉积在间隔物（152）之上和之间的空间中。 使共聚物自组织，每个嵌段物质与相同类型的其它嵌段物种聚集。