Invention Grant
- Patent Title: Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
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Application No.: US15807102Application Date: 2017-11-08
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Publication No.: US10446479B2Publication Date: 2019-10-15
- Inventor: Pandi C. Marimuthu , Yaojian Lin , Kang Chen , Yu Gu , Won Kyoung Choi
- Applicant: STATS ChipPAC Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/00 ; H01L23/31 ; H01L21/48 ; H01L21/56 ; H01L23/538 ; H01L25/10 ; H01L21/683 ; H01L25/065 ; H01L23/13 ; H01L23/14

Abstract:
A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die.
Public/Granted literature
- US20180068937A1 Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units Public/Granted day:2018-03-08
Information query
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