Invention Grant
- Patent Title: Field-effect transistors with dual thickness gate dielectrics
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Application No.: US16699566Application Date: 2019-11-30
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Publication No.: US11145732B2Publication Date: 2021-10-12
- Inventor: Ayan Kar , Kalyan C. Kolluru , Nicholas A. Thomson , Mark Armstrong , Sameer Jayanta Joglekar , Rui Ma , Sayan Saha , Hyuk Ju Ryu , Akm A. Ahsan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/423 ; H01L27/02 ; H01L29/40 ; H01L29/08

Abstract:
Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.
Public/Granted literature
- US20210167180A1 FIELD-EFFECT TRANSISTORS WITH DUAL THICKNESS GATE DIELECTRICS Public/Granted day:2021-06-03
Information query
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