公开(公告)号：US20210167180A1

公开(公告)日：2021-06-03

申请号：US16699566

申请日：2019-11-30

申请人： Intel Corporation

发明人： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Mark Armstrong ,  Sameer Jayanta Joglekar ,  Rui Ma ,  Sayan Saha ,  Hyuk Ju Ryu ,  Akm A. Ahsan

IPC分类号： H01L29/423 ,  H01L27/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/40

摘要： Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

公开(公告)号：US11652107B2

公开(公告)日：2023-05-16

申请号：US16447874

申请日：2019-06-20

申请人： Intel Corporation

发明人： Nicholas Thomson ,  Ayan Kar ,  Kalyan Kolluru ,  Nathan Jack ,  Rui Ma ,  Mark Bohr ,  Rishabh Mehandru ,  Halady Arpit Rao

IPC分类号： H01L29/06 ,  H01L27/12 ,  H01L27/02 ,  H01L21/84 ,  H01L29/861

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0255 ,  H01L27/1211 ,  H01L29/8613

摘要： Embodiments include diode devices and transistor devices. A diode device includes a first fin region over a first conductive region and an insulator region, and a second fin region over a second conductive and insulator regions, where the second fin region is laterally adjacent to the first fin region, and the insulator region is between the first and second conductive regions. The diode device includes a first conductive via on the first conductive region, where the first conductive via is vertically adjacent to the first fin region, and a second conductive via on the second conductive region, where the second conductive via is vertically adjacent to the second fin region. The diode device may include conductive contacts, first portions on the first fin region, second portions on the second fin region, and gate electrodes between the first and second portions and the conductive contacts.

公开(公告)号：US20210202472A1

公开(公告)日：2021-07-01

申请号：US16728111

申请日：2019-12-27

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Adam Clay Faust ,  Frank Patrick O'Mahony ,  Ayan Kar ,  Rui Ma

IPC分类号： H01L27/02

摘要： Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

公开(公告)号：US20230402449A1

公开(公告)日：2023-12-14

申请号：US18457453

申请日：2023-08-29

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Adam Clay Faust ,  Frank Patrick O'Mahony ,  Ayan Kar ,  Rui Ma

IPC分类号： H01L27/02

CPC分类号： H01L27/0292 ,  H01L27/0288 ,  H01L27/0255

摘要： Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

公开(公告)号：US11791331B2

公开(公告)日：2023-10-17

申请号：US17526199

申请日：2021-11-15

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Adam Clay Faust ,  Frank Patrick O'Mahony ,  Ayan Kar ,  Rui Ma

IPC分类号： H01L27/02

CPC分类号： H01L27/0292 ,  H01L27/0255 ,  H01L27/0288

摘要： Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

公开(公告)号：US20220415877A1

公开(公告)日：2022-12-29

申请号：US17358934

申请日：2021-06-25

申请人： Intel Corporation

发明人： Benjamin Orr ,  Rohit Grover ,  Nathan Jack ,  Nicholas Thomson ,  Rui Ma ,  Ayan Kar ,  Kalyan Kolluru

IPC分类号： H01L27/02 ,  H01L27/088

摘要： A semiconductor device includes a first interconnect and a second interconnect, a substrate between the first and second interconnects and one or more wells on the substrate on a first level. A second level includes a first fin and a second fin, each on the one or more wells, where the first fin and the one or more wells include dopants of a first conductivity type and the second fin includes a dopant of a second conductivity type. A third fin is over a first region between the substrate and the first interconnect, and a fourth fin is over a second region between the substrate and the second interconnect. A third interconnect is electrically coupled between the first interconnect and the first fin and a fourth interconnect is electrically coupled between the second interconnect and the second fin.

公开(公告)号：US20220077140A1

公开(公告)日：2022-03-10

申请号：US17526199

申请日：2021-11-15

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Adam Clay Faust ,  Frank Patrick O'Mahony ,  Ayan Kar ,  Rui Ma

IPC分类号： H01L27/02

摘要： Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

公开(公告)号：US11145732B2

公开(公告)日：2021-10-12

申请号：US16699566

申请日：2019-11-30

申请人： Intel Corporation

发明人： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Mark Armstrong ,  Sameer Jayanta Joglekar ,  Rui Ma ,  Sayan Saha ,  Hyuk Ju Ryu ,  Akm A. Ahsan

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L27/02 ,  H01L29/40 ,  H01L29/08

摘要： Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.