公开(公告)号：US20210167180A1

公开(公告)日：2021-06-03

申请号：US16699566

申请日：2019-11-30

申请人： Intel Corporation

发明人： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Mark Armstrong ,  Sameer Jayanta Joglekar ,  Rui Ma ,  Sayan Saha ,  Hyuk Ju Ryu ,  Akm A. Ahsan

IPC分类号： H01L29/423 ,  H01L27/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/40

摘要： Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

公开(公告)号：US20240088132A1

公开(公告)日：2024-03-14

申请号：US17943819

申请日：2022-09-13

申请人： Intel Corporation

发明人： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Ayan Kar ,  Chu-Hsin Liang ,  Benjamin Orr ,  Biswajeet Guha ,  Brian Greene ,  Chung-Hsun Lin ,  Sabih U. Omar ,  Sameer Jayanta Joglekar

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/861

CPC分类号： H01L27/0255 ,  H01L29/0673 ,  H01L29/8611

摘要： An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.

公开(公告)号：US11145732B2

公开(公告)日：2021-10-12

申请号：US16699566

申请日：2019-11-30

申请人： Intel Corporation

发明人： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Mark Armstrong ,  Sameer Jayanta Joglekar ,  Rui Ma ,  Sayan Saha ,  Hyuk Ju Ryu ,  Akm A. Ahsan

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L27/02 ,  H01L29/40 ,  H01L29/08

摘要： Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.