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    VERTICAL DIODES IN STACKED TRANSISTOR TECHNOLOGIES
    3.
    发明申请
    VERTICAL DIODES IN STACKED TRANSISTOR TECHNOLOGIES 有权

    公开(公告)号：US20230089395A1

    公开(公告)日：2023-03-23

    申请号：US17448373

    申请日：2021-09-22

    申请人： INTEL CORPORATION

    发明人： Benjamin Orr ,  Nicholas A. Thomson ,  Ayan Kar ,  Nathan D. Jack ,  Kalyan C. Kolluru ,  Patrick Morrow ,  Cheng-Ying Huang ,  Charles C. Kuo

    IPC分类号： H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

    摘要： Integrated circuits including vertical diodes. In an example, a first transistor is above a second transistor. The first transistor includes a first semiconductor body extending laterally from a first source or drain region. The first source or drain region includes one of a p-type dopant or an n-type dopant. The second transistor includes a second semiconductor body extending laterally from a second source or drain region. The second source or drain region includes the other of the p-type dopant or the n-type dopant. The first source or drain region and second source or drain region are at least part of a diode structure, which may have a PN junction (e.g., first and second source/drain regions are merged) or a PIN junction (e.g., first and second source/drain regions are separated by an intrinsic semiconductor layer, or a dielectric layer and the first and second semiconductor bodies are part of the junction).

    Gate-all-around integrated circuit structures including varactors
    7.
    发明授权
    Gate-all-around integrated circuit structures including varactors 有权

    公开(公告)号：US11417781B2

    公开(公告)日：2022-08-16

    申请号：US16830112

    申请日：2020-03-25

    申请人： Intel Corporation

    发明人： Ayan Kar ,  Saurabh Morarka ,  Carlos Nieva-Lozano ,  Kalyan Kolluru ,  Biswajeet Guha ,  Chung-Hsun Lin ,  Brian Greene ,  Tahir Ghani

    IPC分类号： H01L29/93 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

    摘要： Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

    INTEGRATED CIRCUIT STRUCTURES INCLUDING BACKSIDE VIAS
    8.
    发明申请
    INTEGRATED CIRCUIT STRUCTURES INCLUDING BACKSIDE VIAS 有权

    公开(公告)号：US20210202472A1

    公开(公告)日：2021-07-01

    申请号：US16728111

    申请日：2019-12-27

    申请人： Intel Corporation

    发明人： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Adam Clay Faust ,  Frank Patrick O'Mahony ,  Ayan Kar ,  Rui Ma

    IPC分类号： H01L27/02

    摘要： Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

    TRANSISTOR DEVICES WITH EXTENDED DRAIN
    9.
    发明公开
    TRANSISTOR DEVICES WITH EXTENDED DRAIN 审中-公开

    公开(公告)号：US20240088136A1

    公开(公告)日：2024-03-14

    申请号：US17943557

    申请日：2022-09-13

    申请人： Intel Corporation

    发明人： Ayan Kar ,  Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Benjamin Orr

    IPC分类号： H01L27/02

    CPC分类号： H01L27/027

    摘要： An integrated circuit structure includes a sub-fin, a source region in contact with a first portion of the sub-fin, and a drain region in contact with a second portion of the sub-fin. A body including semiconductor material is above the sub-fin, where the body extends laterally between the source region and the drain region. A gate structure is on the body and includes (i) a gate electrode, and (ii) a gate dielectric between the gate electrode and the body. In an example, a first distance between the drain region and the gate electrode is at least two times a second distance between the source region and the gate electrode, where the first and second distances are measured in a same horizontal plane that runs in a direction parallel to the body. In an example, the body is a nanoribbon, a nanosheet, a nanowire, or a fin.

    VARACTOR DEVICE WITH BACKSIDE ELECTRICAL CONTACT
    10.
    发明公开
    VARACTOR DEVICE WITH BACKSIDE ELECTRICAL CONTACT 审中-公开

    公开(公告)号：US20230420578A1

    公开(公告)日：2023-12-28

    申请号：US17848660

    申请日：2022-06-24

    申请人： Intel Corporation

    发明人： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Vijaya Bhaskara Neeli ,  Said Rami ,  Saurabh Morarka ,  Karthik Krishaswamy ,  Mauro J. Kobrinsky

    IPC分类号： H01L29/93 ,  H01L29/06 ,  H01L29/417

    CPC分类号： H01L29/93 ,  H01L29/0673 ,  H01L29/417 ,  H01L29/42392

    摘要： A varactor device includes a support structure, an electrically conductive layer at the backside of the support structure, two semiconductor structures including doped semiconductor materials, two contact structures, and a semiconductor region. Each contract structure is electrically conductive and is connected to a different one of the semiconductor structures A contract structure couples the corresponding semiconductor structure to the electrically conductive layer. The semiconductor region is between the two semiconductor structures and can be connected to the two semiconductor structures. The semiconductor region may include non-planar semiconductor structures coupled with a gate. The gate may be coupled to another electrically conductive layer at the frontside of the support structure. The varactor device may further include a pair of additional semiconductor regions that are electrically insulated from each other. The additional semiconductor regions may be coupled to two oppositely polarized gates, respectively.