公开(公告)号：US11145732B2

公开(公告)日：2021-10-12

申请号：US16699566

申请日：2019-11-30

申请人： Intel Corporation

发明人： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Mark Armstrong ,  Sameer Jayanta Joglekar ,  Rui Ma ,  Sayan Saha ,  Hyuk Ju Ryu ,  Akm A. Ahsan

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L27/02 ,  H01L29/40 ,  H01L29/08

摘要： Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

公开(公告)号：US11728335B2

公开(公告)日：2023-08-15

申请号：US16257855

申请日：2019-01-25

申请人： Intel Corporation

发明人： Guannan Liu ,  Akm A. Ahsan ,  Mark Armstrong ,  Bernhard Sell

IPC分类号： H01L27/07 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/0705 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

公开(公告)号：US20210167180A1

公开(公告)日：2021-06-03

申请号：US16699566

申请日：2019-11-30

申请人： Intel Corporation

发明人： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Mark Armstrong ,  Sameer Jayanta Joglekar ,  Rui Ma ,  Sayan Saha ,  Hyuk Ju Ryu ,  Akm A. Ahsan

IPC分类号： H01L29/423 ,  H01L27/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/40

摘要： Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.