- 专利标题: Memory devices with four data line bias levels
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申请号: US17396825申请日: 2021-08-09
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公开(公告)号: US11562791B1公开(公告)日: 2023-01-24
- 发明人: Hao T. Nguyen , Tomoko Ogura Iwasaki , Erwin E. Yu , Dheeraj Srinivasan , Sheyang Ning , Lawrence Celso Miranda , Aaron S. Yip , Yoshihiko Kamata
- 申请人: MICRON TECHNOLOGY, INC.
- 申请人地址: US ID Boise
- 专利权人: MICRON TECHNOLOGY, INC.
- 当前专利权人: MICRON TECHNOLOGY, INC.
- 当前专利权人地址: US ID Boise
- 代理机构: Dicke, Billig & Czaja, PLLC
- 主分类号: G11C16/04
- IPC分类号: G11C16/04 ; G11C16/10 ; G11C16/34 ; G11C16/26 ; G11C11/56
摘要:
Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.
公开/授权文献
- US20230039026A1 MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS 公开/授权日:2023-02-09
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