公开(公告)号：US11875861B2

公开(公告)日：2024-01-16

申请号：US17980871

申请日：2022-11-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang H. Siau ,  Hao T. Nguyen

IPC: G11C16/30 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/3404 ,  G11C16/0425 ,  G11C16/26 ,  G11C16/30

Abstract: Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

公开(公告)号：US20230162793A1

公开(公告)日：2023-05-25

申请号：US18095049

申请日：2023-01-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  G11C16/26 ,  G11C11/5671

Abstract: Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.

公开(公告)号：US20230039026A1

公开(公告)日：2023-02-09

申请号：US17396825

申请日：2021-08-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

公开(公告)号：US11508444B2

公开(公告)日：2022-11-22

申请号：US17199524

申请日：2021-03-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang H. Siau ,  Hao T. Nguyen

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C16/30

Abstract: Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

公开(公告)号：US11915758B2

公开(公告)日：2024-02-27

申请号：US18095049

申请日：2023-01-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C11/5621 ,  G11C11/5671

Abstract: Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.

公开(公告)号：US20230046283A1

公开(公告)日：2023-02-16

申请号：US17980871

申请日：2022-11-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang H. Siau ,  Hao T. Nguyen

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/30 ,  G11C16/26

Abstract: Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

公开(公告)号：US11562791B1

公开(公告)日：2023-01-24

申请号：US17396825

申请日：2021-08-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56

Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

公开(公告)号：US20220208283A1

公开(公告)日：2022-06-30

申请号：US17199524

申请日：2021-03-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chang H. Siau ,  Hao T. Nguyen

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04

Abstract: Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.