A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.