公开(公告)号：US20240379847A1

公开(公告)日：2024-11-14

申请号：US18784241

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H01L29/78 ,  G11C5/06 ,  G11C11/22 ,  H01L21/28 ,  H01L29/51 ,  H01L29/786

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

公开(公告)号：US11710790B2

公开(公告)日：2023-07-25

申请号：US17150522

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: G11C11/22 ,  H01L29/78 ,  G11C5/06 ,  H01L29/786 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/78391 ,  G11C5/063 ,  G11C11/223 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/7869

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

公开(公告)号：US20240379778A1

公开(公告)日：2024-11-14

申请号：US18780868

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H01L21/28 ,  G11C11/22 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

公开(公告)号：US20240155845A1

公开(公告)日：2024-05-09

申请号：US18413668

申请日：2024-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： TsuChing Yang ,  Hung-Chang Sun ,  Kuo Chang Chiang ,  Sheng-Chih Lai ,  Yu-Wei Jiang

IPC: H10B51/20 ,  G11C11/22 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  G11C11/2255 ,  G11C11/2257 ,  H10B51/10 ,  H10B51/30

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a layer stack over a substrate, where the layer stack includes alternating layers of a first dielectric material and a word line (WL) material; forming first trenches extending vertically through the layer stack; filling the first trenches, where filling the first trenches includes forming, in the first trenches, a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material; after filling the first trenches, forming second trenches extending vertically through the layer stack, the second trenches being interleaved with the first trenches; and filling the second trenches, where filling the second trenches includes forming, in the second trenches, the ferroelectric material, the channel material over the ferroelectric material, and the second dielectric material over the channel material.

公开(公告)号：US20210408045A1

公开(公告)日：2021-12-30

申请号：US17119409

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H01L27/11597 ,  H01L27/12 ,  G11C11/22 ,  H01L29/66 ,  H01L29/786

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

公开(公告)号：US20250120091A1

公开(公告)日：2025-04-10

申请号：US18985411

申请日：2024-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H10B51/20 ,  H10B51/10 ,  H10D30/67

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

公开(公告)号：US11903214B2

公开(公告)日：2024-02-13

申请号：US17316167

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： TsuChing Yang ,  Hung-Chang Sun ,  Kuo Chang Chiang ,  Sheng-Chih Lai ,  Yu-Wei Jiang

IPC: H10B51/20 ,  H10B51/30 ,  G11C11/22 ,  H10B51/10

CPC classification number: H10B51/20 ,  G11C11/2255 ,  G11C11/2257 ,  H10B51/10 ,  H10B51/30

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a layer stack over a substrate, where the layer stack includes alternating layers of a first dielectric material and a word line (WL) material; forming first trenches extending vertically through the layer stack; filling the first trenches, where filling the first trenches includes forming, in the first trenches, a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material; after filling the first trenches, forming second trenches extending vertically through the layer stack, the second trenches being interleaved with the first trenches; and filling the second trenches, where filling the second trenches includes forming, in the second trenches, the ferroelectric material, the channel material over the ferroelectric material, and the second dielectric material over the channel material.

公开(公告)号：US11729987B2

公开(公告)日：2023-08-15

申请号：US17119409

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H10B51/20 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  G11C11/22

CPC classification number: H10B51/20 ,  G11C11/223 ,  H01L27/1225 ,  H01L29/66742 ,  H01L29/7869

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

公开(公告)号：US20230253464A1

公开(公告)日：2023-08-10

申请号：US18301113

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H01L21/28 ,  G11C11/22 ,  H01L29/78 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L29/40111 ,  G11C11/223 ,  G11C11/2255 ,  H01L29/78391 ,  H01L29/516 ,  H01L29/7869 ,  G11C11/2257

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

公开(公告)号：US11856781B2

公开(公告)日：2023-12-26

申请号：US17194715

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： TsuChing Yang ,  Hung-Chang Sun ,  Kuo Chang Chiang ,  Sheng-Chih Lai ,  Yu-Wei Jiang

IPC: H10B51/20 ,  H01L29/06 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/0649 ,  H10B51/10

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.