公开(公告)号：US20240379847A1

公开(公告)日：2024-11-14

申请号：US18784241

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H01L29/78 ,  G11C5/06 ,  G11C11/22 ,  H01L21/28 ,  H01L29/51 ,  H01L29/786

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

公开(公告)号：US12057495B2

公开(公告)日：2024-08-06

申请号：US18326682

申请日：2023-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-Sheng Huang ,  Hung-Chang Sun ,  I-Ming Chang ,  Zi-Wei Fang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/08 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02661 ,  H01L21/02675 ,  H01L21/31116 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/30604

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.

公开(公告)号：US11710790B2

公开(公告)日：2023-07-25

申请号：US17150522

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: G11C11/22 ,  H01L29/78 ,  G11C5/06 ,  H01L29/786 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/78391 ,  G11C5/063 ,  G11C11/223 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/7869

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

公开(公告)号：US10707333B2

公开(公告)日：2020-07-07

申请号：US16191244

申请日：2018-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-Sheng Huang ,  Hung-Chang Sun ,  I-Ming Chang ,  Zi-Wei Fang

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L21/306

Abstract: A method includes following steps. A dummy gate structure is formed across a first portion of a semiconductor fin. A doped semiconductor layer is formed across a second portion of the semiconductor fin. A dielectric layer is formed across the doped semiconductor layer. An interface between the dielectric layer and the doped semiconductor layer substantially conforms to a profile of a combination of a top surface and sidewalls of the semiconductor fin. The dummy gate structure is replaced with a metal gate structure.

公开(公告)号：US11856781B2

公开(公告)日：2023-12-26

申请号：US17194715

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： TsuChing Yang ,  Hung-Chang Sun ,  Kuo Chang Chiang ,  Sheng-Chih Lai ,  Yu-Wei Jiang

IPC: H10B51/20 ,  H01L29/06 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/0649 ,  H10B51/10

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.

公开(公告)号：US20230317848A1

公开(公告)日：2023-10-05

申请号：US18330604

申请日：2023-06-07

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H01L29/78 ,  G11C5/06 ,  H01L29/786 ,  G11C11/22 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/78391 ,  G11C5/063 ,  H01L29/7869 ,  G11C11/223 ,  H01L29/40111 ,  H01L29/516

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

公开(公告)号：US11373902B2

公开(公告)日：2022-06-28

申请号：US16888929

申请日：2020-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Chang Sun ,  Po-Chin Chang ,  Akira Mineji ,  Zi-Wei Fang ,  Pinyen Lin

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088

Abstract: A semiconductor structure includes a semiconductor substrate, a gate structure, an etch stop layer, a dielectric structure, and a conductive material. The gate structure is on the semiconductor substrate. The etch stop layer is over the gate structure. The dielectric structure is over the etch stop layer, in which the dielectric structure has a ratio of silicon to nitrogen varying from a middle layer of the dielectric structure to a bottom layer of the dielectric structure. The conductive material extends through the dielectric structure.

公开(公告)号：US20210375936A1

公开(公告)日：2021-12-02

申请号：US17150522

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/786 ,  H01L27/1159 ,  G11C5/06

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

公开(公告)号：US11024723B2

公开(公告)日：2021-06-01

申请号：US16920197

申请日：2020-07-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-Sheng Huang ,  Hung-Chang Sun ,  I-Ming Chang ,  Zi-Wei Fang

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L21/306

Abstract: A semiconductor includes a substrate, a semiconductor fin, an STI structure, a fin sidewall spacer, and a doped silicon layer. The semiconductor fin extends from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The fin sidewall spacer extends along a middle portion of the semiconductor fin that is above the lower portion of the semiconductor fin. The doped silicon layer wraps around three sides of an upper portion of the semiconductor fin that is above the middle portion of the semiconductor fin.

公开(公告)号：US20240379778A1

公开(公告)日：2024-11-14

申请号：US18780868

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H01L21/28 ,  G11C11/22 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).