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公开(公告)号：US20230317848A1
公开(公告)日：2023-10-05
申请号：US18330604
申请日：2023-06-07
CPC分类号： H01L29/78391 , G11C5/063 , H01L29/7869 , G11C11/223 , H01L29/40111 , H01L29/516
摘要： A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.
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公开(公告)号：US20210375936A1
公开(公告)日：2021-12-02
申请号：US17150522
申请日：2021-01-15
IPC分类号： H01L27/11597 , H01L27/11587 , H01L29/786 , H01L27/1159 , G11C5/06
摘要： A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.
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3.发明授权公开(公告)号：US11723210B2
公开(公告)日：2023-08-08
申请号：US17333300
申请日：2021-05-28
发明人： Tsu Ching Yang , Feng-Cheng Yang , Sheng-Chih Lai , Yu-Wei Jiang , Kuo-Chang Chiang , Hung-Chang Sun , Chen-Jun Wu , Chung-Te Lin
摘要： In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.
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公开(公告)号：US20210408045A1
公开(公告)日：2021-12-30
申请号：US17119409
申请日：2020-12-11
IPC分类号： H01L27/11597 , H01L27/12 , G11C11/22 , H01L29/66 , H01L29/786
摘要： A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.
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公开(公告)号：US11710790B2
公开(公告)日：2023-07-25
申请号：US17150522
申请日：2021-01-15
CPC分类号： H01L29/78391 , G11C5/063 , G11C11/223 , H01L29/40111 , H01L29/516 , H01L29/7869
摘要： A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.
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公开(公告)号：US20230337437A1
公开(公告)日：2023-10-19
申请号：US18341116
申请日：2023-06-26
IPC分类号： H10B51/20 , H01L27/12 , H01L29/786 , H01L29/66 , G11C11/22
CPC分类号： H10B51/20 , H01L27/1225 , H01L29/7869 , H01L29/66742 , G11C11/223
摘要： A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.
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7.发明申请公开(公告)号：US20220285395A1
公开(公告)日：2022-09-08
申请号：US17333300
申请日：2021-05-28
发明人： Tsu Ching Yang , Feng-Cheng Yang , Sheng-Chih Lai , Yu-Wei Jiang , Kuo-Chang Chiang , Hung-Chang Sun , Chen-Jun Wu , Chung-Te Lin
IPC分类号： H01L27/11597 , H01L27/1159
摘要： In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.
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公开(公告)号：US20210408044A1
公开(公告)日：2021-12-30
申请号：US17119346
申请日：2020-12-11
IPC分类号： H01L27/11597 , H01L27/11587 , H01L29/78 , H01L29/786 , G11C11/22
摘要： A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).
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公开(公告)号：US11729987B2
公开(公告)日：2023-08-15
申请号：US17119409
申请日：2020-12-11
IPC分类号： H10B51/20 , H01L27/12 , H01L29/786 , H01L29/66 , G11C11/22
CPC分类号： H10B51/20 , G11C11/223 , H01L27/1225 , H01L29/66742 , H01L29/7869
摘要： A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.
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公开(公告)号：US20230253464A1
公开(公告)日：2023-08-10
申请号：US18301113
申请日：2023-04-14
IPC分类号： H01L21/28 , G11C11/22 , H01L29/78 , H01L29/51 , H01L29/786
CPC分类号： H01L29/40111 , G11C11/223 , G11C11/2255 , H01L29/78391 , H01L29/516 , H01L29/7869 , G11C11/2257
摘要： A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).
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