Invention Publication
- Patent Title: POWER-ON-RESET SIGNAL ISOLATION DURING LOWER POWER MODE
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Application No.: US18060114Application Date: 2022-11-30
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Publication No.: US20230205305A1Publication Date: 2023-06-29
- Inventor: Venkateswar Kowkutla , Chunhua Hu , Raghavendra Santhanagopal , Kazunobu Shin , Charles Gerlach , Rejitha Nair , Ritesh Sojitra , Sai Rajaraman , Anthony Seely , Siva Srinivas Kothamasu , Varun Singh , John Apostol
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Main IPC: G06F1/3287
- IPC: G06F1/3287 ; G06F13/16 ; G06F13/40 ; G06F13/42
Abstract:
A circuit device is provided and includes a first power domain comprising a universal serial bus (USB) subsystem and/or a memory controller subsystem. The first power domain is configured to isolate the USB subsystem and/or the memory controller subsystem from a power-on-reset signal asserted during a low power mode.
Information query
IPC分类:
