-
公开(公告)号：US12271289B2
公开(公告)日：2025-04-08
申请号：US18403293
申请日：2024-01-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Raghavendra Santhanagopal , Chunhua Hu , Anthony Frederick Seely , Nishanth Menon , Rajesh Kumar Vanga , Rejitha Nair , Siva Srinivas Kothamasu , Kazunobu Shin , Jason Peck , John Apostol
IPC: G06F9/44 , G06F9/4401 , G06F11/30 , G06F11/362 , G06F13/10
Abstract: A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.
-
公开(公告)号：US20230205305A1
公开(公告)日：2023-06-29
申请号：US18060114
申请日：2022-11-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Chunhua Hu , Raghavendra Santhanagopal , Kazunobu Shin , Charles Gerlach , Rejitha Nair , Ritesh Sojitra , Sai Rajaraman , Anthony Seely , Siva Srinivas Kothamasu , Varun Singh , John Apostol
IPC: G06F1/3287 , G06F13/16 , G06F13/40 , G06F13/42
CPC classification number: G06F1/3287 , G06F13/1668 , G06F13/4068 , G06F13/423
Abstract: A circuit device is provided and includes a first power domain comprising a universal serial bus (USB) subsystem and/or a memory controller subsystem. The first power domain is configured to isolate the USB subsystem and/or the memory controller subsystem from a power-on-reset signal asserted during a low power mode.
-
公开(公告)号：US09471140B2
公开(公告)日：2016-10-18
申请号：US14304795
申请日：2014-06-13
IPC: G06F1/32
CPC classification number: G06F1/3296 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171 , Y02D10/172
Abstract: A system having multiple power mode types, for example, includes a power manager that is responsive to a selection of a suspend power mode type for maintaining processor context information in volatile memory while the processor is in the selected suspend mode. A status register is arranged to retain the status of the context information in the volatile memory while the processor is in the selected suspend power mode. The power manager is arranged to selectively apply power to various voltage domains in response to the type of power mode selected. The processor is optionally arranged to signal the power manager of transitions to the selected suspend mode and of transitions to an active mode using a power enable signal.
Abstract translation: 例如，具有多个功率模式类型的系统包括功率管理器，该功率管理器响应于在处理器处于所选择的挂起模式时在易失性存储器中维持处理器上下文信息的暂停功率模式类型的选择。 状态寄存器被布置成在处理器处于选择的挂起电源模式时将上下文信息的状态保持在易失性存储器中。 功率管理器被布置为响应于所选择的功率模式的类型选择性地向各个电压域施加功率。 处理器可选地布置成使用功率使能信号向功率管理器发信号通知转换到所选择的暂停模式和转换到活动模式。
-
公开(公告)号：US20250015698A1
公开(公告)日：2025-01-09
申请号：US18897219
申请日：2024-09-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Kazunobu Shin , Venkateswara Pothireddy , Siva Kothamasu , John Apostol , Raghavendra Santhanagopal , Rajagopal Kollengode Ananthanarayanan , Rejitha Nair , Charles Gerlach , Ravi Teja Reddy
Abstract: In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.
-
公开(公告)号：US11899563B2
公开(公告)日：2024-02-13
申请号：US17686348
申请日：2022-03-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Raghavendra Santhanagopal , Chunhua Hu , Anthony Frederick Seely , Nishanth Menon , Rajesh Kumar Vanga , Rejitha Nair , Siva Srinivas Kothamasu , Kazunobu Shin , Jason Peck , John Apostol
IPC: G06F13/10 , G06F11/36 , G06F9/4401 , G06F11/30
CPC classification number: G06F11/3656 , G06F9/4401 , G06F11/3048 , G06F13/102 , G06F2201/86 , G06F2213/0038
Abstract: A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.
-
Patent Agency Ranking
公开(公告)号：US20150362987A1
公开(公告)日：2015-12-17
申请号：US14304795
申请日：2014-06-13
IPC: G06F1/32
CPC classification number: G06F1/3296 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/171 , Y02D10/172
Abstract: A system having multiple power mode types, for example, includes a power manager that is responsive to a selection of a suspend power mode type for maintaining processor context information in volatile memory while the processor is in the selected suspend mode. A status register is arranged to retain the status of the context information in the volatile memory while the processor is in the selected suspend power mode. The power manager is arranged to selectively apply power to various voltage domains in response to the type of power mode selected. The processor is optionally arranged to signal the power manager of transitions to the selected suspend mode and of transitions to an active mode using a power enable signal.
Abstract translation: 例如，具有多个功率模式类型的系统包括功率管理器，该功率管理器响应于在处理器处于所选择的挂起模式时在易失性存储器中维持处理器上下文信息的暂停功率模式类型的选择。 状态寄存器被布置成在处理器处于选择的挂起电源模式时将上下文信息的状态保持在易失性存储器中。 功率管理器被布置为响应于所选择的功率模式的类型选择性地向各个电压域施加功率。 处理器可选地布置成使用功率使能信号向功率管理器发信号通知转换到所选择的暂停模式和转换到活动模式。
-
公开(公告)号：US12132386B2
公开(公告)日：2024-10-29
申请号：US18160308
申请日：2023-01-27
Applicant: Texas Instruments Incorporated
Inventor： Venkateswar Kowkutla , Kazunobu Shin , Venkateswara Pothireddy , Siva Kothamasu , John Apostol , Raghavendra Santhanagopal , Rajagopal Kollengode Ananthanarayanan , Rejitha Nair , Charles Gerlach , Ravi Teja Reddy
CPC classification number: H02M1/0032 , H02M3/04
Abstract: In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.
-
公开(公告)号：US20240134776A1
公开(公告)日：2024-04-25
申请号：US18403293
申请日：2024-01-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Raghavendra Santhanagopal , Chunhua Hu , Anthony Frederick Seely , Nishanth Menon , Rajesh Kumar Vanga , Rejitha Nair , Siva Srinivas Kothamasu , Kazunobu Shin , Jason Peck , John Apostol
IPC: G06F11/36 , G06F9/4401 , G06F11/30 , G06F13/10
CPC classification number: G06F11/3656 , G06F9/4401 , G06F11/3048 , G06F13/102 , G06F2201/86 , G06F2213/0038
Abstract: A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.
-
公开(公告)号：US20230238872A1
公开(公告)日：2023-07-27
申请号：US18160308
申请日：2023-01-27
Applicant: Texas Instruments Incorporated
Inventor： Venkateswar Kowkutla , Kazunobu Shin , Venkateswara Pothireddy , Siva Kothamasu , John Apostol , Raghavendra Santhanagopal , Rajagopal Kollengode Ananthanarayanan , Rejitha Nair , Charles Gerlach , Ravi Teja Reddy
CPC classification number: H02M1/0032 , H02M3/04
Abstract: In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.
-
公开(公告)号：US20230205672A1
公开(公告)日：2023-06-29
申请号：US17686348
申请日：2022-03-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Kowkutla , Raghavendra Santhanagopal , Chunhua Hu , Anthony Frederick Seely , Nishanth Menon , Vanga Kumar Rajesh , Rejitha Nair , Siva Srinivas Kothamasu , Kazunobu Shin , Jason Peck , John Apostol
IPC: G06F11/36 , G06F9/4401 , G06F11/30 , G06F13/10
CPC classification number: G06F11/3656 , G06F9/4401 , G06F11/3048 , G06F13/102 , G06F2201/86 , G06F2213/0038
Abstract: A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.021 seconds)
