Invention Application
- Patent Title: TECHNOLOGIES FOR BARRIER LAYERS IN PEROVSKITE TRANSISTORS
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Application No.: US18345127Application Date: 2023-06-30
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Publication No.: US20250006841A1Publication Date: 2025-01-02
- Inventor: Arnab Sen Gupta , Dmitri Evgenievich Nikonov , John J. Plombon , Rachel A. Steinhardt , Punyashloka Debashis , Kevin P. O'Brien , Matthew V. Metz , Scott B. Clendenning , Brandon Holybee , Marko Radosavljevic , Ian Alexander Young , I-Cheng Tung , Sudarat Lee , Raseong Kim , Pratyush P. Buragohain
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/221 ; H01L29/423 ; H01L29/775 ; H01L29/786

Abstract:
Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.
Information query
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