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    Semiconductor integrated circuit device and method of producing the same using master slice approach
    1.
    发明公开
    Semiconductor integrated circuit device and method of producing the same using master slice approach 失效
    Integrierte Halbleiterschaltungsanordnung vom“Masterslice”-Typ und Herstellungsverfahrendafür。

    公开(公告)号：EP0338817A2

    公开(公告)日：1989-10-25

    申请号：EP89303912.3

    申请日：1989-04-20

    申请人： FUJITSU LIMITED

    发明人： Hirose, Yoshio ,  Yamashita, Koichi ,  Kawahara, Shigeki ,  Sato, Shinji ,  Sasaki, Takeshi ,  Kumagai, Ataru

    IPC分类号： H01L27/02 ,  H01L23/52 ,  H01L21/82

    CPC分类号： H01L23/528 ,  H01L21/82 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device includes: a master chip(203) including a basic cell region(201) having a plurality of basic cell arrays(206) arranged thereon, and an input/output cell region(202) having a plurality of input/output cells(207) arranged along the periphery of the basic cell region; a first wiring layer formed on the basic cell region and the input/output cell region via a first insulation layer having contact holes at predetermined positions, the first wiring layer including fixed wirings(LA,508); and a second wiring layer formed on the first wiring layer via a second insulation layer having through holes at predetermined positions, the second wiring layer including programmed wirings(LB,507). Only the wiring pattern of the second wiring layer is suitably changed in accordance with conditions of circuits applied to the input/output cell region and the basic cell region in regions corresponding to the input/output cell region and the basic cell region, thereby greatly reducing a turnaround time of the device.

    摘要翻译： 一种半导体集成电路器件，包括：主芯片（203），包括具有布置在其上的多个基本单元阵列（206）的基本单元区域（201），以及具有多个输入/ 输出单元（207），沿着基本单元区域的周边布置; 经由具有在预定位置具有接触孔的第一绝缘层形成在基本单元区域和输入/输出单元区域上的第一布线层，第一布线层包括固定布线（LA，508）; 以及第二布线层，其经由在预定位置具有通孔的第二绝缘层形成在所述第一布线层上，所述第二布线层包括编程布线（LB，507）。 根据与输入/输出单元区域和基本单元区域对应的区域中的输入/输出单元区域和基本单元区域的电路的条件适当地改变第二布线层的布线图案，从而大大降低 设备的周转时间。

    A masterslice semiconductor device
    2.
    发明公开
    A masterslice semiconductor device 失效
    MASTERSLICE半导体器件

    公开(公告)号：EP0133958A3

    公开(公告)日：1985-12-27

    申请号：EP84108860

    申请日：1984-07-26

    申请人： FUJITSU LIMITED

    发明人： Sato, Shinji ,  Goto, Gensuke

    IPC分类号： H01L27/02

    CPC分类号： H01L21/82 ,  H01L27/11807 ,  Y10S257/923

    摘要： A layout technology of a masterslice semiconductor device is disclosed, which reduces the unused redundant transistors. In the basic cells of the masterslice semiconductor device, each of the transistors is formed to be electrically independent from others; i.e., each transistor has an individual gate electrode and occupies an individual region for the source and drain. The terminals formed in parallel to the conduction channel of a relevant transistor permits to interconnect substantially any electrodes in a basic cell array by a straight wiring line. Such straight interconnection reduces the effective number of wiring channels for constituting a unit cell, and facilitates to construct a larger scale unit cell in a basic cell array.

    A masterslice semiconductor device
    3.
    发明公开
    A masterslice semiconductor device 失效
    一种masterslice半导体器件

    公开(公告)号：EP0133958A2

    公开(公告)日：1985-03-13

    申请号：EP84108860.2

    申请日：1984-07-26

    申请人： FUJITSU LIMITED

    发明人： Sato, Shinji ,  Goto, Gensuke

    IPC分类号： H01L27/02

    CPC分类号： H01L21/82 ,  H01L27/11807 ,  Y10S257/923

    摘要： A layout technology of a masterslice semiconductor device is disclosed, which reduces the unused redundant transistors. In the basic cells of the masterslice semiconductor device, each of the transistors is formed to be electrically independent from others; i.e., each transistor has an individual gate electrode and occupies an individual region for the source and drain. The terminals formed in parallel to the conduction channel of a relevant transistor permits to interconnect substantially any electrodes in a basic cell array by a straight wiring line. Such straight interconnection reduces the effective number of wiring channels for constituting a unit cell, and facilitates to construct a larger scale unit cell in a basic cell array.

    摘要翻译： 公开了一种母板半导体器件的布局技术，其减少了未使用的冗余晶体管。 在主母片半导体器件的基本单元中，每个晶体管被形成为与其他电学独立; 即，每个晶体管具有单独的栅电极并且占据用于源极和漏极的单独区域。 与相关晶体管的导电沟道平行形成的端子允许通过直线布线基本上互连基本单元阵列中的任何电极。 这种直接互连减少了构成单位单元的配线通道的有效数量，并且便于在基本单元阵列中构建更大规模的单位单元。

    Gate array large scale integrated circuit devices
    4.
    发明公开
    Gate array large scale integrated circuit devices 失效
    门阵列大规模集成电路设备

    公开(公告)号：EP0093003A3

    公开(公告)日：1986-01-08

    申请号：EP83302324

    申请日：1983-04-22

    申请人： FUJITSU LIMITED

    发明人： Matsumura, Nobutake Nisshin Dai-2 ,  Sato, Shinji

    IPC分类号： H01L27/02

    CPC分类号： H01L22/00 ,  H01L24/05 ,  H01L27/11898 ,  H01L2224/05553 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

    摘要： Gate array LSI's are produced with the aid of a standard layout pattern defining a basic cell array region (2), on which internal cell arrays are arranged, and a peripheral circuit region (3), arranged on the periphery of the basic cell array region. The peripheral circuit region comprises input/output cell regions (7), for constructing an input buffer circuit and a part of an output circuit, and a general purpose cell array region (4) which can be used for constructing remaining parts of the output buffer circuit. Where the general purpose cell array region is not used in the construction of such a buffer circuit it can be used for constructing various other desired circuits. Thus greater design flexibility is made available.

    Semiconductor integrated circuit device and method of producing the same using master slice approach
    7.
    发明公开
    Semiconductor integrated circuit device and method of producing the same using master slice approach 失效
    半导体集成电路装置及其使用主狭缝方法生产相同方法

    公开(公告)号：EP0338817A3

    公开(公告)日：1992-05-06

    申请号：EP89303912.3

    申请日：1989-04-20

    申请人： FUJITSU LIMITED

    发明人： Hirose, Yoshio ,  Yamashita, Koichi ,  Kawahara, Shigeki ,  Sato, Shinji ,  Sasaki, Takeshi ,  Kumagai, Ataru

    IPC分类号： H01L27/02 ,  H01L23/52 ,  H01L21/82

    CPC分类号： H01L23/528 ,  H01L21/82 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device includes: a master chip(203) including a basic cell region(201) having a plurality of basic cell arrays(206) arranged thereon, and an input/output cell region(202) having a plurality of input/output cells(207) arranged along the periphery of the basic cell region; a first wiring layer formed on the basic cell region and the input/output cell region via a first insulation layer having contact holes at predetermined positions, the first wiring layer including fixed wirings(LA,508); and a second wiring layer formed on the first wiring layer via a second insulation layer having through holes at predetermined positions, the second wiring layer including programmed wirings(LB,507). Only the wiring pattern of the second wiring layer is suitably changed in accordance with conditions of circuits applied to the input/output cell region and the basic cell region in regions corresponding to the input/output cell region and the basic cell region, thereby greatly reducing a turnaround time of the device.