公开(公告)号：EP0439310A2

公开(公告)日：1991-07-31

申请号：EP91300435.4

申请日：1991-01-19

申请人： FUJITSU LIMITED

发明人： Yamazaki, Hirokazu ,  Yoshida, Masanobu

IPC分类号： H03K19/003

CPC分类号： G11C8/18 ,  G11C7/22 ,  H03K19/00361

摘要： A semiconductor device for absorbing a noise comprises a first (12) and second (14) buffer. The first and second buffers receive an external signal (S) having a rising edge and a falling edge, and performs waveform shaping thereof to produce an output signal. The first buffer (12), which issues an output signal (Sa) for controlling the internal circuits of a chip of the semiconducteur device so as to make the chip's internal circuits active/stand-by, is not sensitive to the rising edge of the external signal (S), but is sensitive to the falling edge of the same external signal. The second buffer (14), which issues an output signal (Sb) for controlling an output circuit of a chip of the semiconductor device so as to make the output circuit active/stand-by, is sensistive to both the rising and the falling edges of the external signal.

摘要翻译： 用于吸收噪声的半导体器件包括第一缓冲器（12）和第二缓冲器（14）。 第一和第二缓冲器接收具有上升沿和下降沿的外部信号（S），并且执行其波形整形以产生输出信号。 发出用于控制半导体器件的芯片的内部电路以使芯片的内部电路有效/待机的输出信号（Sa）的第一缓冲器（12）对于上升沿不敏感 外部信号（S），但对同一外部信号的下降沿敏感。 发出用于控制半导体器件的芯片的输出电路以使输出电路有效/待机的输出信号（Sb）的第二缓冲器（14）对上升沿和下降沿都是敏感的 的外部信号。

公开(公告)号：EP0935256B1

公开(公告)日：2002-05-08

申请号：EP99105448.7

申请日：1994-02-08

申请人： FUJITSU LIMITED

发明人： Kumakura, Sinsuke ,  Yamazaki, Hirokazu ,  Watanabe, Hisayoshi ,  Kasa, Yasushi

IPC分类号： G11C29/00 ,  H01L21/02

CPC分类号： G11C29/021 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

摘要： An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3,..., whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

公开(公告)号：EP0439310B1

公开(公告)日：1996-04-03

申请号：EP91300435.4

申请日：1991-01-19

申请人： FUJITSU LIMITED

发明人： Yamazaki, Hirokazu ,  Yoshida, Masanobu

IPC分类号： H03K19/003

CPC分类号： G11C8/18 ,  G11C7/22 ,  H03K19/00361

公开(公告)号：EP0986066A2

公开(公告)日：2000-03-15

申请号：EP99108018.5

申请日：1999-04-23

申请人： FUJITSU LIMITED

发明人： Ono,Chikai ,  Yamazaki, Hirokazu

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric memory includes memory cells, a pair of bit lines to which the memory cells are connected, and a control circuit which changes a reference cell applied to one of the pair of bit lines while data read from one of the memory cells is output to the other one of the pair of bit lines.

摘要翻译： 铁电存储器包括存储器单元，存储单元连接到的一对位线，以及控制电路，其将从一个存储单元读取的数据输出到对应于一对位线之一的参考单元， 这对位线中的另一个。

公开(公告)号：EP0439310A3

公开(公告)日：1991-11-13

申请号：EP91300435.4

申请日：1991-01-19

申请人： FUJITSU LIMITED

发明人： Yamazaki, Hirokazu ,  Yoshida, Masanobu

IPC分类号： H03K19/003

CPC分类号： G11C8/18 ,  G11C7/22 ,  H03K19/00361

摘要： A semiconductor device for absorbing a noise comprises a first (12) and second (14) buffer. The first and second buffers receive an external signal (S) having a rising edge and a falling edge, and performs waveform shaping thereof to produce an output signal. The first buffer (12), which issues an output signal (Sa) for controlling the internal circuits of a chip of the semiconducteur device so as to make the chip's internal circuits active/stand-by, is not sensitive to the rising edge of the external signal (S), but is sensitive to the falling edge of the same external signal. The second buffer (14), which issues an output signal (Sb) for controlling an output circuit of a chip of the semiconductor device so as to make the output circuit active/stand-by, is sensistive to both the rising and the falling edges of the external signal.

公开(公告)号：EP0986066A3

公开(公告)日：2000-09-13

申请号：EP99108018.5

申请日：1999-04-23

申请人： FUJITSU LIMITED

发明人： Ono,Chikai ,  Yamazaki, Hirokazu

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric memory includes memory cells, a pair of bit lines to which the memory cells are connected, and a control circuit which changes a reference cell applied to one of the pair of bit lines while data read from one of the memory cells is output to the other one of the pair of bit lines.

摘要翻译： 铁电存储器包括存储单元，存储单元所连接到的一对位线以及控制电路，该控制电路在将从一个存储单元读取的数据输出到一对存储单元的同时将施加到一对位线之一的参考单元 该对位线中的另一个。

公开(公告)号：EP0935256A1

公开(公告)日：1999-08-11

申请号：EP99105448.7

申请日：1994-02-08

申请人： FUJITSU LIMITED

发明人： Kumakura, Sinsuke ,  Yamazaki, Hirokazu ,  Watanabe, Hisayoshi ,  Kasa, Yasushi

IPC分类号： G11C29/00 ,  H01L21/02

CPC分类号： G11C29/021 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

摘要： A test method for a writable nonvolatile semiconductor memory, comprising: a writing step for writing data; an aging step wherein the nonvolatile semiconductor memory is placed under prescribed aging conditions; and a verification step where data is read out and compared with the data written in the writing step for verification. The test method is characterised in that the aging step incorporates a step of forming a coating film for alleviating the stress applied to the nonvolatile semiconductor memory during assembly.

摘要翻译： 本发明的一个目的是提供一种允许容易和有效测试的半导体器件。 非易失性半导体存储器包括字线WLi和位线BLi，由非易失性存储单元Cij组成的存储单元矩阵17，读出放大器15，用于执行写和擦除操作所需的定时控制的写/擦除定时电路9，以及 状态寄存器2，用于在电路9的操作完成时存储存储器的工作状态，其中在存储单元矩阵17的地址外提供两种虚拟单元D1，D2，D3。 它们的值被固定到从感测放大器15引起不同输出的不同值。通过访问虚拟单元来产生通过条件或失败条件。