公开(公告)号：EP0071042B1

公开(公告)日：1989-10-18

申请号：EP82105997.9

申请日：1982-07-06

申请人： International Business Machines Corporation

发明人： Malaviya, Shashi Dhar

IPC分类号： G11C11/34

CPC分类号： G11C11/34 ,  H01L27/1025

公开(公告)号：EP0205008A3

公开(公告)日：1988-01-20

申请号：EP86107011

申请日：1986-05-23

申请人： International Business Machines Corporation

发明人： Malaviya, Shashi Dhar

IPC分类号： H01L29/06 ,  H01L21/308 ,  H01L29/72 ,  H01L29/36 ,  H01L29/76

CPC分类号： H01L21/0337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L29/0657

摘要： Disclosed is a submicron-wide single-crystal silicon structure protruding form a monolithic silicon body (32). This three-dimensional structure includes a lower section (68) of a first (N) conductivity type and an upper section (50) of a second (P) conductivity type. The upper section (50), consisting of narrow top and bottom portions (70, 72) separated by a relatively wide middle portion (56), consitutes the silicon material from which various active or passive integrated circuit devices may be fabricated. For example, in the case of an NPN transistor, the central region of the middle portion (56) constitutes the base region, the emitter and collector being enbed- ded in the two outer side regions thereof in a mutually facing relationship. Electrical contacts to the elements of the structure are established on the top and/or Isides of the protrusion. Owing to its freestanding self-isolated characteristic, dielectric isolation of the device is not necessary. Alternatively, total dielectric isolation of the IC may be achieved by utilizing a dielectric material for the bottom of the protrusion. Disclosed also is a process of fabricating the above structure. In one embodiment, starting with a single crystal N silicon body (32) having a P region, an insulator stud (48) of submicron width and length dictated by the limits of lithography is formed on the P region. Using the stud (48) as a mask, the P 'region is etched forming a narrow top portion (70) having the stud width projecting from the silicon body (32). On the exposed sides of the top portion - (70) oxide walls (52, 54) are formed and the etching continued forming the middle portion (56) of a width exceeding that of the top portion (70). An oxide-nitride wall (58, 60) is established on the exposed sides of the middle portion (56) and, using the resulting structure as a mask, the etching is continued to completely etch through the P region and a substantial portion of the underlying N silicon body - (32) thereby forming a free-standing silicon protrusion structure. By thermal oxidation, thick oxide walls (64, 66) are then formed on the just exposed sides of the silicon. Alternatively, the exposed sides of silicon may be completely oxidized to obtain a fully dielectrically isolated silicon protruding structure.

公开(公告)号：EP0220392A2

公开(公告)日：1987-05-06

申请号：EP86110459.4

申请日：1986-07-29

申请人： International Business Machines Corporation

发明人： Goth, George Richard ,  Malaviya, Shashi Dhar

IPC分类号： H01L27/10 ,  H01L21/82

CPC分类号： H01L27/10861 ,  H01L21/762 ,  H01L27/1023 ,  H01L27/10829

摘要： A high density integrated circuit structure, for example a dynamic memory cell, is described which includes an active/passive device in combination with a capacitor structure. The capacitor structure is of the polysilicon-oxide-silicon type and is formed on the sidewalls of a mesa-shaped and dielectrically isolated region of silicon material resulting from the formation of an isolation trench in the silicon. The trench is filled with a plastic material, such as polyimide. The capacitor is formed by the isolated region of silicon material (14) which functions as the first capacitor plate, a doped polysilicon layer (22a) provided on the vertical walls of the mesa serving as the second capacitor plate and a thin dielectric layer (21) interposed between the two plates serving as the capacitor's dielectric. Since the poly­silicon is wrapped around the periphery of the mesa as a coating on the vertical sidewalls thereof, it gives rise to a large storage capacitance without an increase in the cell size.

公开(公告)号：EP0071042A3

公开(公告)日：1986-06-04

申请号：EP82105997

申请日：1982-07-06

申请人： International Business Machines Corporation

发明人： Malaviya, Shashi Dhar

IPC分类号： G11C11/34

CPC分类号： G11C11/34 ,  H01L27/1025

摘要： An electronic data storage or memory array having DC stable memory cells which utilize the principle of a unique substrate biasing mechanism, whereby a channel region defined by resistive substrate material and formed under a controlled electrode (20) becomes "pinched off' and, in the process, so affects the DC potential at that electrode as to maintain the pinched off condition. Consequently, the memory cell becomes established in a first DC stable state ("one" state). The principle is preferably embodied in a field effect transistor (22), the resistive channel region being connected in a DC conductive path to a fixed resistor (R1) and a potential source (+V). Accordingly, when appropriate signal levels representing a binary "one" are applied to word and bit lines (WL1, BL1) connected to a first controlling, or gate, electrode and to a second controlling electrode, respectively, of the FET, the described pinch-off occurs, with concomitantly high resistance (R2) in the DC path, such that the potential adjacent the controlled electrode (20) is maintained in the "one" state that was initiated by the signals on the word and bit lines. On the other hand, when signals representing a "zero" are applied to the same controlling electrodes, the resistive channel region (R2) under the controlled electrode (20) is no longer pinched-off, whereby the memory cell becomes established in the second or "zero" DC stable state. Means for reading the stored data in the cell are integrated with the cell.

公开(公告)号：EP0043942A2

公开(公告)日：1982-01-20

申请号：EP81104797.6

申请日：1981-06-23

申请人： International Business Machines Corporation

发明人： Goth, George Richard ,  Magdo, Ingrid Emese ,  Malaviya, Shashi Dhar

IPC分类号： H01L21/60 ,  H01L21/28 ,  H01L21/00 ,  H01L21/31

CPC分类号： H01L21/76897 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/28 ,  H01L29/41 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions and, more particularly self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub- micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body (50, 51) and then forming a first insulating layer (52) on a major surface of the silicon body. A layer of polycrystalline silicon (53) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer (55) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (56) on the major surface of the silicon body (50). The remaining polycrystalline silicon layer (53) is then removed by etching to leave the narrow dimensioned regions (56) on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between. A blanket layer of a plastic material over the conductive layer to planarize the surface is accomplished. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions (56) are reached leaving the structure of patterns (59 to 64) of metal filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less.

摘要翻译： 一种用于形成具有狭窄尺寸的电介质区域的图案的集成电路的方法，并且更具体的自对准金属过程被描述其实现自对准金属硅接触和亚微米接触到接触和金属 - 金属间距 ， 触点与金属之间的绝缘是具有一微米或更小的数量级的厚度尺寸的介电材料的图案。 所述金属或介电结构是基本平坦的。 形成具有这种结构的集成电路的方法包括提供硅体（50，51），然后形成在硅主体的主表面上的第一绝缘层（52）。 多晶硅（53）的层上形成在那里。 开口中通过反应离子蚀刻，这导致结构具有基本水平表面和基本垂直的表面上的多晶硅层制成。 然后，第二绝缘层（55）形成在两个基本水平的表面和基本垂直的表面。 该第二绝缘层的反应离子蚀刻去除基本上水平层和提供区域的上硅本体（50）的主表面的窄尺寸的介电图案（56）。 剩余的多晶硅层（53）然后，通过蚀刻到离开窄尺寸的区域（56）的所述硅体的主表面上除去。 导电层是毯desposited过其间的窄尺寸的区域和地区。 塑料材料在导电层以平坦化表面的覆盖层来完成。 继续反应离子蚀刻所述塑料材料和导电层直到窄尺寸的区域的顶部（56）在达到离开的具有厚度尺寸金属的图案（59至64）填充介电材料的图案之间的区域中的结构 在微米或更小的数量级。

公开(公告)号：EP0220392B1

公开(公告)日：1993-05-05

申请号：EP86110459.4

申请日：1986-07-29

申请人： International Business Machines Corporation

发明人： Goth, George Richard ,  Malaviya, Shashi Dhar

IPC分类号： H01L27/10 ,  H01L21/82

CPC分类号： H01L27/10861 ,  H01L21/762 ,  H01L27/1023 ,  H01L27/10829

公开(公告)号：EP0253087B1

公开(公告)日：1993-01-20

申请号：EP87106897.9

申请日：1987-05-12

申请人： International Business Machines Corporation

发明人： Bhatia, Harsaran Singh ,  Jones, Harry Jordan ,  Malaviya, Shashi Dhar

IPC分类号： H03K19/086 ,  H03K19/082 ,  H02H3/38 ,  G05F1/20

CPC分类号： H03K19/1738 ,  H03K19/086

公开(公告)号：EP0137195B1

公开(公告)日：1988-01-13

申请号：EP84109400.6

申请日：1984-08-08

申请人： International Business Machines Corporation

发明人： Malaviya, Shashi Dhar ,  Srinivasan, Gurumakonda Ramasamiengar

IPC分类号： H01L21/76 ,  H01L21/205

CPC分类号： H01L21/76205 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639

公开(公告)号：EP0137195A1

公开(公告)日：1985-04-17

申请号：EP84109400.6

申请日：1984-08-08

申请人： International Business Machines Corporation

发明人： Malaviya, Shashi Dhar ,  Srinivasan, Gurumakonda Ramasamiengar

IPC分类号： H01L21/76 ,  H01L21/205

CPC分类号： H01L21/76205 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639

摘要： A method of integrated circuit fabrication and the resulting integrated circuit wherein areas (8) of recessed oxide isolation surround active device regions (3) and the bird's head (101) and bird's beak formed during formation of the recessed oxide regions (8) is eliminated by forming a deep dielectric isolation trench (9) directly over the bird's head (101). A very thin epitaxial layer (10) can be provided over the active device regions (3) of the integrated circuit. Preferably, the thin epitaxial layer (10) is selectively grown only over active device regions (3). Also, in later manufacturing steps, metal (31) is deposited in direct registration with contact areas.

摘要翻译： 消除了集成电路制造的方法和所得到的集成电路，其中消除了在形成凹陷氧化物区域（8）期间形成的围绕有源器件区域（3）和鸟头（101）和鸟嘴的凹陷氧化物隔离区域（8） 通过直接在鸟的头部（101）上形成深介电隔离沟槽（9）。 可以在集成电路的有源器件区域（3）上提供非常薄的外延层（10）。 优选地，薄外延层（10）仅选择性地生长在有源器件区域（3）上。 此外，在后续制造步骤中，金属（31）与接触区域直接对准地沉积。

公开(公告)号：EP0043004A2

公开(公告)日：1982-01-06

申请号：EP81104437.9

申请日：1981-06-10

申请人： International Business Machines Corporation

发明人： Malaviya, Shashi Dhar

IPC分类号： G11C11/34

CPC分类号： G11C11/39

摘要： The storage is fabricated in integrated circuit form, typically on a semiconductor chip, each storage cell being contained within a single isolated zone formed in the semiconductor chip. Each storage cell is DC stable and operates on a conductivity modulation principle, i.e. a cell conducts when it stores a binary "1" and the conductive state is maintained by conductivity modulation of an element of the cell, and the cell is non-conducting when storing a binary "0". In its most basic form, each cell includes at least two resistors (R2, R2'; R3, R3', R2"') formed in series in a P type semiconductor region (18, 20). At least one of the resistors, formed in a lightly doped portion of the P type region, is a variable resistor (R2, R2", R2"') having both high and low values of resistance. The high value of resistance is changed to a low value of resistance by injecting electrons from a proximate N type semiconductor region. The low value of resistance is then maintained by the current conducted through the storage cell during standby.

摘要翻译： 存储器以集成电路形式制造，通常在半导体芯片上，每个存储单元被包含在形成在半导体芯片中的单个隔离区域内。 每个存储单元是DC稳定的，并且以电导率调制原理运行，即，当存储二进制“1”时，单元传导，并且通过该单元的元件的导电性调制维持导通状态，并且该单元不导通 存储二进制“0”。 在其最基本的形式中，每个单元包括在P型半导体区域（18,20）中串联形成的至少两个电阻器（R2，R2min; R3，R3min，R2“'）。 形成在P型区域的轻掺杂部分中的电阻器中的至少一个是具有高电阻值和低电阻值的可变电阻器（R2，R2sec，R2“）。 通过从邻近的N型半导体区域注入电子，电阻的高值被改变为低的电阻值。 然后通过在待机期间通过存储单元传导的电流来维持电阻的低值。