公开(公告)号：EP2972914A4

公开(公告)日：2016-11-30

申请号：EP14770419

申请日：2014-03-06

申请人： MICRON TECHNOLOGY INC

发明人： MIRICHIGNI GRAZIANO ,  BALLUCHI DANIELE ,  PORZIO LUCA

IPC分类号： G06F13/16

CPC分类号： G06F3/0611 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/068 ,  G06F13/161 ,  G06F13/1689 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/22 ,  G11C8/06 ,  G11C2207/2209 ,  G11C2207/2272 ,  G11C2207/229

摘要： Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to receive an activate command indicative of a type of a command during a first addressing phase and to receive the command during a second addressing phase. The memory may further be configured to provide information indicating that the memory is not available to perform a command responsive, at least in part, to receiving the command during a variable latency period and to provide information indicating that the memory is available to perform a command responsive, at least in part, to receiving the command after the variable latency period.

公开(公告)号：EP2742506A1

公开(公告)日：2014-06-18

申请号：EP12823364.0

申请日：2012-08-13

申请人： GSI Technology Inc.

发明人： HAIG, Robert ,  CHUANG, Patrick ,  TSENG, Chih ,  HUANG, Mu-hsiang

IPC分类号： G11C11/409

CPC分类号： G11C11/40615 ,  G06F13/1615 ,  G11C7/1039 ,  G11C7/1072 ,  G11C11/419 ,  G11C2207/2281 ,  G11C2207/229

摘要： Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

公开(公告)号：EP1269473B1

公开(公告)日：2014-06-11

申请号：EP01924470.6

申请日：2001-03-30

申请人： Round Rock Research, LLC

发明人： ROOHPARVAR, Frankie, F.

IPC分类号： G11C8/18 ,  G06F13/16 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C7/106 ,  G06F13/1615 ,  G06F13/1668 ,  G06F13/1694 ,  G06F13/4243 ,  G11C7/10 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/18 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/105 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2216/22

公开(公告)号：EP2056301B1

公开(公告)日：2011-11-30

申请号：EP09151003.2

申请日：2001-06-29

申请人： Mosaid Technologies Incorporated

发明人： Demone, Paul

IPC分类号： G11C11/406 ,  G11C7/22

CPC分类号： G11C11/408 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/18 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/2281 ,  G11C2207/229

公开(公告)号：EP1807766A4

公开(公告)日：2009-07-22

申请号：EP05731247

申请日：2005-03-31

申请人： ANALOG DEVICES INC

发明人： HOLLIS PAUL W ,  LATTIMORE GEORGE M ,  RUTLEDGE MATTHEW B

IPC分类号： G06F12/00 ,  G06F13/16 ,  G11C7/10

CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/1072 ,  G11C7/222 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229

摘要： A de-coupled memory access system (50) including a memory access control circuit (52) configured to generate first and second independent, de-coupled time references. The memory access control circuit (52) includes a read initiate circuit (54) responsive to the first time reference (58) and a read signal for generating a read-enable signal (66), and a write initiate circuit (58) responsive to the second time reference (60) and a write signal for generating a write enable signal (70) independent of the read enable signal for providing independent, de-coupled write access to a memory array (80).

公开(公告)号：EP2056301A3

公开(公告)日：2009-06-17

申请号：EP09151003.2

申请日：2001-06-29

申请人： Mosaid Technologies Incorporated

发明人： Demone, Paul

IPC分类号： G11C11/406 ,  G11C7/22

CPC分类号： G11C11/408 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/18 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/2281 ,  G11C2207/229

摘要： A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

公开(公告)号：EP0918333B1

公开(公告)日：2007-11-28

申请号：EP98107272.1

申请日：1998-04-21

申请人： FUJITSU LIMITED

发明人： Saito, Miyoshi, c/o Fujitsu Limited ,  Ogawa, Junji, c/o Fujitsu Limited

IPC分类号： G11C7/00 ,  H04L25/08 ,  H04L25/497

CPC分类号： G11C7/1063 ,  G11C7/04 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/229 ,  H04L25/03878

公开(公告)号：EP1180799A3

公开(公告)日：2005-09-28

申请号：EP01119605.2

申请日：2001-08-17

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Ohsawa, Takashi

IPC分类号： H01L27/108 ,  H01L27/12 ,  G11C11/4076 ,  G11C11/406 ,  G11C11/404

CPC分类号： H01L29/7841 ,  G11C7/02 ,  G11C7/18 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2211/4016 ,  H01L21/84 ,  H01L21/845 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/785

摘要： A memory cell MC comprises one MOS transistor having a floating bulk region which is electrically isolated from others. A gate electrode 13 of the MOS transistor is connected to a word line WL, a drain diffusion region 14 thereof is connected to a bit line BL, and a source diffusion region 15 thereof is connected to a fixed potential line SL. The memory cell stores a first threshold state in which majority carriers produced by impact ionization are injected and held in the bulk region 12 of the MOS transistor and a second threshold state in which the majority carriers in the bulk region 12 of the MOS transistor are emitted by a forward bias at a pn junction on the drain side as binary data. Thereby, a semiconductor memory device in which a simple transistor structure is used as a memory cell, enabling dynamic storage of binary data by a small number of signal lines can be provided.

摘要翻译： 存储单元MC包括具有与其它电气隔离的浮动块区的一个MOS晶体管。 MOS晶体管的栅电极13连接到字线WL，其漏极扩散区域14连接到位线BL，其源极扩散区域15连接到固定电位线SL。 存储单元存储第一阈值状态，其中通过冲击电离产生的多数载流子被注入并保持在MOS晶体管的体区域12中，并且第二阈值状态，其中MOS晶体管的体区12中的多数载流子被发射 通过在漏极侧的pn结处的正向偏压作为二进制数据。 因此，可以提供一种半导体存储器件，其中使用简单的晶体管结构作为存储单元，能够通过少量信号线实现二进制数据的动态存储。

公开(公告)号：EP3149732B1

公开(公告)日：2018-12-26

申请号：EP15728248.4

申请日：2015-05-14

申请人： SanDisk Technologies LLC

发明人： ELLIS, Robert W. ,  HIGGINS, James M. ,  MOHAN, Vidyabhushan

IPC分类号： G11C5/14 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G06F12/02 ,  G11C16/04 ,  G11C16/10 ,  G11C29/02 ,  G11C29/04

CPC分类号： G11C16/10 ,  G06F12/0246 ,  G11C5/14 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/4076 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/32 ,  G11C16/349 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2207/2281 ,  G11C2207/229

摘要： The embodiments described herein are used to execute staggered memory operations. The method includes, at each of a plurality of distinct memory portions of the storage device, establishing a non-zero command delay parameter distinct from a command delay parameter established for one or more of the other memory portions in the plurality of distinct memory portions. The method further includes, after establishing the non-zero command delay parameter in each of the plurality of distinct memory portions of the storage device, executing memory operations in two or more of the plurality of distinct memory portions of the storage device during overlapping time periods, the executing including, in each memory portion of the plurality of memory portions, delaying execution of a respective memory operation by an amount of time corresponding to the command delay parameter established for that memory portion.

公开(公告)号：EP3149732A1

公开(公告)日：2017-04-05

申请号：EP15728248.4

申请日：2015-05-14

申请人： SanDisk Technologies LLC

发明人： ELLIS, Robert W. ,  HIGGINS, James M. ,  MOHAN, Vidyabhushan

IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G06F12/02

CPC分类号： G11C16/10 ,  G06F12/0246 ,  G11C5/14 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/4076 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/32 ,  G11C16/349 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2207/2281 ,  G11C2207/229

摘要： The embodiments described herein are used to execute staggered memory operations. The method includes, at each of a plurality of distinct memory portions of the storage device, establishing a non-zero command delay parameter distinct from a command delay parameter established for one or more of the other memory portions in the plurality of distinct memory portions. The method further includes, after establishing the non-zero command delay parameter in each of the plurality of distinct memory portions of the storage device, executing memory operations in two or more of the plurality of distinct memory portions of the storage device during overlapping time periods, the executing including, in each memory portion of the plurality of memory portions, delaying execution of a respective memory operation by an amount of time corresponding to the command delay parameter established for that memory portion.

摘要翻译： 这里描述的实施例用于执行交错存储器操作。 该方法包括在存储设备的多个不同的存储器部分的每一个处，建立不同于为多个不同存储器部分中的一个或多个其他存储器部分建立的命令延迟参数的非零命令延迟参数。 该方法还包括：在存储设备的多个不同存储器部分的每一个中建立非零命令延迟参数之后，在重叠时间段期间在存储设备的多个不同存储器部分的两个或更多个不同存储器部分中执行存储器操作 执行在多个存储器部分的每个存储器部分中包括延迟相应存储器操作的执行时间对应于为该存储器部分建立的命令延迟参数。