公开(公告)号：EP4426077A3

公开(公告)日：2024-11-13

申请号：EP24188063.2

申请日：2015-08-20

申请人： LG Innotek Co., Ltd.

发明人： BAE, Yun Mi ,  KWON, Soon Gyu ,  KIM, Sang Hwa ,  LEE, Sang Young ,  LEE, Jin Hak ,  LEE, Han Su ,  JEONG, Dong Hun ,  JEONG, In Ho ,  CHOI, Dae Young ,  HWANG, Jung Ho

IPC分类号： H05K3/10 ,  H05K3/24

摘要： A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.

公开(公告)号：EP4452595A1

公开(公告)日：2024-10-30

申请号：EP23701418.8

申请日：2023-01-19

申请人： Dr. Schneider Kunststoffwerke GmbH I.INS.

发明人： KÜFNER, Mario ,  SCHINZLER, Claus ,  BAIER, Ralf

IPC分类号： B29C45/00 ,  B29C45/16 ,  B60Q3/00 ,  H05K3/10

公开(公告)号：EP3145283B1

公开(公告)日：2024-10-30

申请号：EP15793610.5

申请日：2015-05-14

发明人： YOSHIDA, Manabu ,  UEMURA, Sei ,  NOBESHIMA, Taiki

IPC分类号： H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K3/10 ,  B32B25/10 ,  H01B5/00 ,  H01B5/02 ,  H01B5/14 ,  H01B7/06 ,  H01B13/00 ,  H01R11/01 ,  H05K3/14

公开(公告)号：EP4415490A1

公开(公告)日：2024-08-14

申请号：EP21959971.9

申请日：2021-10-08

申请人： Fuji Corporation

发明人： TOMINAGA, Ryojiro

IPC分类号： H05K3/10

CPC分类号： H05K3/10

摘要： A circuit forming method including: an acquiring step of acquiring metal-containing liquid information including at least one of a density of a metal-containing liquid containing metal fine particles or a content of the metal fine particles; a calculating step of calculating the number of layers of the metal-containing liquid required to form a wiring by stacking the metal-containing liquid, based on the metal-containing liquid information acquired in the acquiring step; and a wiring forming step of forming a wiring by stacking the metal-containing liquid in the number of layers calculated in the calculating step.

公开(公告)号：EP3941165B1

公开(公告)日：2024-08-07

申请号：EP21183386.8

申请日：2021-07-02

IPC分类号： H05K3/24 ,  C03C17/36 ,  C25D5/02 ,  H05K3/10 ,  H05K1/09 ,  H05K3/12 ,  H05K3/18 ,  C23C18/14 ,  C25D7/12

CPC分类号： C03C17/36 ,  C25D5/02 ,  H05K3/108 ,  H05K1/097 ,  C25D7/123 ,  C03C17/3668 ,  C03C17/3636 ,  H05K2203/10720130101 ,  H05K2201/033820130101

公开(公告)号：EP3845144B1

公开(公告)日：2024-03-20

申请号：EP20217647.5

申请日：2020-12-29

发明人： SHELTON IV, Frederick E. ,  ADAMS, Shane R. ,  ROSS, Nicholas J. ,  HARRIS, Jason L. ,  PATEL, Sudhir B.

IPC分类号： A61B17/072 ,  H05K1/02 ,  A61B17/00 ,  A61B34/30 ,  H05K3/10 ,  H05K1/14 ,  H05K3/12 ,  A61B90/00

公开(公告)号：EP4322712A1

公开(公告)日：2024-02-14

申请号：EP22876625.9

申请日：2022-06-27

申请人： LOTTE ENERGY MATERIALS CORPORATION

发明人： YANG, Chang Yol ,  BEOM, Won Jin ,  KIM, Hyung Cheol ,  SONG, Kideok

IPC分类号： H05K1/09 ,  B32B15/01 ,  H05K3/00 ,  H05K3/10 ,  H05K3/06

摘要： The present invention relates to a carrier-foil-attached ultra-thin copper foil and a method for manufacturing an embedded substrate using same. The carrier-foil-attached ultra-thin copper foil according to the present invention comprises a carrier foil, a non-etched delamination layer on the carrier foil, a first ultra-thin copper foil layer on the non-etched delamination layer, an etching stop layer on the first ultra-thin copper foil layer, and a second ultra-thin copper foil layer on the etching stop layer.

公开(公告)号：EP4285695A1

公开(公告)日：2023-12-06

申请号：EP22701526.0

申请日：2022-01-19

申请人： Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

发明人： PROES, Friedrich

IPC分类号： H05K3/38 ,  C23C18/16 ,  H05K3/10 ,  H05K3/18 ,  H05K1/03

公开(公告)号：EP4187587A1

公开(公告)日：2023-05-31

申请号：EP21845635.8

申请日：2021-07-16

申请人： Kyocera Corporation

发明人： ABE, Yuichi

IPC分类号： H01L23/13 ,  H01L23/12 ,  H01L23/36 ,  H01L25/07 ,  H01L25/18 ,  H05K1/02 ,  H05K1/03 ,  H05K3/10

摘要： A circuit board (1) includes a ceramic substrate (2) having a flat plate shape and a metal plate (3) bonded to one main surface of the ceramic substrate (2) and including a predetermined circuit pattern. An outer peripheral surface (3c) of the metal plate (3) includes a protruding portion (11) protruding outward and a pair of recessed surfaces (12) provided at both sides of the protruding portion (11).

公开(公告)号：EP4064799A1

公开(公告)日：2022-09-28

申请号：EP22151322.9

申请日：2022-01-13

申请人： Intel Corporation

发明人： See, Khai Em ,  Liew, Jia Lin ,  Chuah, Tin Poay ,  Lim, Chee How ,  Ooi, Yi How

IPC分类号： H05K1/02 ,  H05K3/30 ,  H05K3/10 ,  H05K3/00

摘要： Techniques for power tunnels on circuit boards are disclosed. A power tunnel may be created in a circuit board by drilling through non-conductive layers to a conductive trace and then filling in the hole with a conductor. A power tunnel can have a high cross-sectional area and can carry a larger amount of current than an equivalent-width trace, reducing the area on a circuit board required to carry that amount of current.