公开(公告)号：EP1983576A2

公开(公告)日：2008-10-22

申请号：EP08007591.4

申请日：2008-04-18

申请人： Vishay-Siliconix

发明人： Pattanayak, Deva N. ,  Terrill, Kyle ,  Shi, Sharon ,  Lee, Misha ,  Bai, Yuming ,  Lui, Kam ,  Chen, Kuo-In

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/45

CPC分类号： H01L27/0727 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66143 ,  H01L29/66477 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： Remote contacts (1020) to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.

摘要翻译： 与沟槽金属氧化物半导体（MOS）势垒肖特基（TMBS）器件的多晶硅区域的远程触点（1020）以及MOS场效应晶体管（MOSFET）部分的多晶硅区域和TMBS部分的单片 集成TMBS和MOSFET（SKYFET）器件。 多晶硅相对于相邻的台面凹陷。 源极金属与TMBS部分的多晶硅区域的接触是通过将多晶硅延伸到TMBS部分的有源区域之外进行的。 器件结构的这种变化减轻了在接触步骤之前从TMBS部分的多晶硅和硅台面区域中去除所有氧化物的需要。 因此，避免了将接触金属侵入到TMBS器件或SKYFET器件中的沟槽的侧壁中。

公开(公告)号：EP1145327B1

公开(公告)日：2008-04-16

申请号：EP99971151.8

申请日：1999-10-20

申请人： NORTH CAROLINA STATE UNIVERSITY

发明人： BALIGA, Bantval, Jayant

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L27/088 ,  H01L27/095 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/8725 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated power semiconductor devices having improved high frequency switching performance, improved edge termination characteristics and reduced on-state resistance include GD-UMOSFET unit cells with upper trench-based gate electrodes and lower trench-based source electrodes. The use of the trench-based source electrode instead of a larger gate electrode reduces the gate-to-drain capacitance (CGD) of the UMOSFET and improves switching speed by reducing the amount of gate charging and discharging current that is needed during high frequency operation.

公开(公告)号：EP1812971A1

公开(公告)日：2007-08-01

申请号：EP05801556.1

申请日：2005-10-21

申请人： ROBERT BOSCH GMBH

发明人： GOERLACH, Alfred ,  QU, Ning

IPC分类号： H01L29/872 ,  H01L29/861 ,  H01L21/329 ,  H01L29/866

CPC分类号： H01L29/66143 ,  H01L29/0619 ,  H01L29/8611 ,  H01L29/872 ,  H01L29/8725

摘要： The invention relates to a semiconductor device (30) comprising a Schottky diode of the trench-junction-barrier-type with integrated pn diode, and method for producing the same.

公开(公告)号：EP1314207B1

公开(公告)日：2006-03-22

申请号：EP01966385.5

申请日：2001-08-29

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： Hshieh, Fwu-Iuan ,  Chen, Max ,  So, Koon Chong ,  Tsui, Yan Man

IPC分类号： H01L29/872

CPC分类号： H01L29/8725 ,  H01L29/872

摘要： A Schottky rectifier is provided. The Schotttky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.

公开(公告)号：EP1191602A3

公开(公告)日：2004-12-29

申请号：EP01122745.1

申请日：2001-09-21

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： Chih-Wei, Hsu ,  Chung-Min, Liu ,  Ming-Che, Kao ,  Ming-Jinn, Tsai ,  Pu-Ju, Kung

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/331 ,  H01L29/861 ,  H01L29/739 ,  H01L29/06

CPC分类号： H01L29/7813 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/872 ,  H01L29/8725

摘要： A method for fabricating trench MOS devices and termination structure simultaneously is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on the semiconductor substrate prepared. The method comprises following steps: firstly, forming a plurality of first trenches for forming the trench MOS devices in an active region, and a second trench for forming the termination structure. Thereafter, a thermal oxidation process to form a gate oxide on all areas is performed. Then, the first trenches and the second trench are refilled with a first conductive material. An etching back is carried out to remove excess first conductive material so as to form spacer in the second trench and to fill the first trenches only. Next, the gate oxide layer is removed. For IGBT or DMOS device, an extra thermal oxidation and an etching step are required to form inter-conductive oxide layer whereas for Schottky diode, these two steps are skipped. Thereafter, a termination structure oxide layer is formed through deposition, lithographic process and etching. After backside unnecessary layers removal, a sputtering metal layers deposition, lithographic process and etching step are successively performed to form the first electrode with a desired ended location and the second electrode on both side of semiconductor substrate.

摘要翻译： 公开了一种同时制造沟槽MOS器件和端接结构的方法。 MOS器件可以是肖特基二极管，IGBT或DMOS，取决于制备的半导体衬底。 该方法包括以下步骤：首先，在有源区中形成用于形成沟槽MOS器件的多个第一沟槽和用于形成端接结构的第二沟槽。 此后，进行在所有区域上形成栅极氧化物的热氧化工艺。 然后，用第一导电材料再填充第一沟槽和第二沟槽。 进行蚀刻以去除多余的第一导电材料，以便在第二沟槽中形成间隔物并仅填充第一沟槽。 接下来，去除栅极氧化物层。 对于IGBT或DMOS器件，需要额外的热氧化和蚀刻步骤来形成导电氧化物层，而对于肖特基二极管，这两个步骤被跳过。 此后，通过沉积，光刻工艺和蚀刻形成端接结构氧化物层。 在背面不必要的层去除之后，依次进行溅射金属层沉积，光刻处理和蚀刻步骤以形成具有期望的端部位置的第一电极和在半导体衬底两侧的第二电极。

公开(公告)号：EP1191603A3

公开(公告)日：2004-11-17

申请号：EP01122746.9

申请日：2001-09-21

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： Chih-Wei, Hsu ,  Chung-Min, Liu ,  Ming-Che, Kao ,  Ming-Jinn, Tsai ,  Pu-Ju, Kung

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L29/872 ,  H01L29/06 ,  H01L21/336 ,  H01L21/331

CPC分类号： H01L29/7813 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/872 ,  H01L29/8725

摘要： A termination structure for power trench MOS devices is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on what kinds of the semiconductor substrate are prepared. The termination structure comprises: a semiconductor substrate having a trench formed therein; a MOS gate as a spacer formed on a sidewall of the trench; a termination structure oxide layer formed in the trench to cover a portion of the spacer and to cover a bottom of the trench; and a first electrode and a second electrode are, respectively, formed on a bottom surface and upper surface of the semiconductor substrate. The trench is formed from a boundary of the active region to an end of the semiconductor substrate. The trench MOS devices are formed in the active region. In addition for IGBT and DMOS, the second electrode is isolated from MOS gate by an oxide layer; however, for Schottky diode, the second electrode is directed contact to the MOS gate.

摘要翻译： 公开了功率沟槽MOS器件的端接结构。 MOS器件可以是肖特基二极管，IGBT或DMOS，这取决于准备的种类的半导体衬底。 所述端接结构包括：其中形成有沟槽的半导体衬底; 作为形成在沟槽的侧壁上的间隔物的MOS栅极; 形成在所述沟槽中以覆盖所述间隔物的一部分并覆盖所述沟槽的底部的端接结构氧化物层; 并且第一电极和第二电极分别形成在半导体衬底的底表面和上表面上。 沟槽由有源区的边界到半导体衬底的端部形成。 沟槽MOS器件形成在有源区中。 除IGBT和DMOS之外，第二电极通过氧化物层与MOS栅极隔离; 然而，对于肖特基二极管，第二电极被引导接触到MOS栅极。

公开(公告)号：EP1168455A3

公开(公告)日：2004-05-12

申请号：EP01114892.1

申请日：2001-06-29

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Omura, Ichiro, Intellectual Property Division ,  Saito, Wataru, Intellectual Property Division ,  Ogura, Tsuneo, Intellectual Property Division ,  Ohashi, Hiromichi, Intellectual Property Division ,  Saito, Yoshihiko, Intellectual Property Division ,  Tokano, Kenichi, Intellectual Property Division

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7722 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor element of this invention includes a drift layer (12) of a first conductivity type formed on a semiconductor substrate (11) of the first conductivity type, a well layer (13) of a second conductivity type selectively formed in the surface of the drift layer (12), a source layer (14) of the first conductivity type selectively formed in the surface of the well layer (13), a trench (15) formed to reach at least the inside of the drift layer (12) from the surface of the source layer (14) through the well layer (13), a buried electrode (17) formed in the trench (15) through a first insulating film (16), and a control electrode (19) formed on the drift layer (12), the well layer (13), and the source layer (14) through a second insulating film (18).

公开(公告)号：EP1396015A1

公开(公告)日：2004-03-10

申请号：EP02739322.2

申请日：2002-05-22

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： TSUI, Yan, Man ,  HSHIEH, Fwu-Luan ,  SO, Koon, Chong

IPC分类号： H01L21/28 ,  H01L21/44 ,  H01L27/095 ,  H01L29/47 ,  H01L29/82 ,  H01L31/07 ,  H01L31/108

CPC分类号： H01L29/66143 ,  H01L27/0814 ,  H01L29/407 ,  H01L29/872 ,  H01L29/8725

摘要： A Schottky rectifier includes a semiconductor structure having first and second opposing faces (12a and 12b, respectively) each extending to define an active semiconductor region (5) and a termination semiconductor region (10). The structure includes a cathode region (12c) and a drift region (12d) of the first conductivity type adjacent the first and second faces, respectively. The drift region has a lower net doping concentration than that of the cathode region. A plurality of trenches (30) extends from the second face into the semiconductor structure and defines a plurality of mesas (14) therein. At least one of the trenches is located in each of the active and the terminal semiconductor regions. A first insulating region (16) is located adjacent the structure in the plurality of trenches. A second insulating region (45) electrically isolated the active semiconductor region from the terminal semiconductor region. An anode electrode (18) is adjacent to and forms a Schottky rectifying contact with the structure at the second face and is adjacent to the first insulating region in the trenches. The anode electrode electrically connects together the plurality of trenches.

摘要翻译： 肖特基整流器包括具有分别延伸以限定有源半导体区域（5）和终端半导体区域（10）的第一和第二相对面（分别为12a和12b）的半导体结构。 该结构包括分别与第一和第二面相邻的阴极区（12c）和第一导电类型的漂移区（12d）。 漂移区具有比阴极区域更低的净掺杂浓度。 多个沟槽（30）从第二面延伸到半导体结构中并在其中限定多个台面（14）。 至少一个沟槽位于有源半导体区域和终端半导体区域中的每一个中。 第一绝缘区域（16）位于多个沟槽中的结构附近。 第二绝缘区域（45）将有源半导体区域与终端半导体区域电隔离。 阳极电极（18）与第二面上的结构相邻并形成肖特基整流接触，并与沟槽中的第一绝缘区域相邻。 阳极电极将多个沟槽电连接在一起。

公开(公告)号：EP1351313A2

公开(公告)日：2003-10-08

申请号：EP03006486.9

申请日：2003-03-21

申请人： SILICONIX INCORPORATED

发明人： Bhalla, Anup ,  Pitzer, Dorman ,  Korec, Jacek ,  Shi, Xiaorong ,  Lui, Sik

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/8725 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper comers of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

摘要翻译： 在沟槽栅极MIS器件中，沟槽内的栅极接触，从而不需要使栅极材料（通常为多晶硅）延伸到沟槽外部。 这避免了沟槽上部的应力问题。 栅极金属和多晶硅之间的接触通常在位于器件的有源区域之外的栅极金属区域中形成。 描述了用于形成栅极金属和多晶硅之间的接触的各种构造，包括其中沟槽在接触区域中变宽的实施例。 由于在整个器件中多晶硅被回蚀到硅的顶表面之下，通常不需要多晶硅掩模，从而节省制造成本。

公开(公告)号：EP1198843A1

公开(公告)日：2002-04-24

申请号：EP00936410.0

申请日：2000-05-26

申请人： Micro-Ohm Corporation

发明人： BALIGA, Bantval, Jayant

IPC分类号： H01L29/872 ,  H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L21/329 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/42368 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/8725

摘要： Power semiconductor devices having tapered insulating regions include a drift region of first conductivity type therein and first and second trenches in the substrate. The first and second trenches have first and second opposing sidewalls, respectively, that define a mesa therebetween into which the drift region extends. An electrically insulating region having tapered sidewalls is also provided in each of the trenches. The tapered thickness of each of the electrically insulating regions enhances the degree of uniformity of the electric field along the sidewalls of the trenches and in the mesa and allows the power device to support higher blocking voltages despite a high concentration of dopants in the drift region. In particular, an electrically insulating region lines the first sidewall of the first trench and has a nonuniform thickness Tins(y) in a range between about 0.5 and 1.5 times Tideal(y), where Tideal(y)|y>=alpha=epsiins((2epsisEcr/qWmNd)(y-alpha)-¼Wm)/epsis and epsiins is the permittivity of the electrically insulating region, epsis is the permittivity of the drift region, Ecr is the breakdown electric field strength of the drift region, q is the electron charge, Nd is the first conductivity type doping concentration in the drift region, Wm is a width of the mesa, y is the depth, relative to a top of the first trench, at which the thickness of the electrically insulating region is being determined and alpha is a constant. The constant alpha may equal zero in the event the power device is a Schottky rectifier and may equal the depth of the P-base region/N-drift region junction in the event the power device is a vertical MOSFET.