公开(公告)号：EP1882274A2

公开(公告)日：2008-01-30

申请号：EP06750663.4

申请日：2006-04-19

申请人： Cree Inc.

发明人： RYU, Sei-Hyung ,  JENNY, Jason, R. ,  DAS, Mrinal, K. ,  HOBGOOD, Hudson, McDonald ,  AGARWAL, Anant, K. ,  PALMOUR, John, W.

IPC分类号： H01L29/87 ,  H01L29/74 ,  H01L29/739 ,  H01L29/06 ,  H01L29/24 ,  H01L21/04

CPC分类号： H01L29/66068 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/747 ,  H01L29/87 ,  H01L2924/10156

摘要： High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer, has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface of the voltage blocking SiC substrate. A third region of SiC is provided on the second SiC layer and has the second conductivity type. A fourth region of SiC is provided in the second SiC layer, has the first conductivity type and is adjacent to the third region of SiC. First and second contacts are provided on the first and third regions of SiC, respectively. Related methods of fabricating high voltage SiC devices are also provided.

摘要翻译： 高电压碳化硅（SiC）器件，例如，晶闸管，提供。 设置在电压阻断具有第二导电类型的SiC衬底的第一表面上具有第一导电类型的第一SiC层。 SiC的第一区域被设置在第一SiC层上，并具有第二导电类型。 SiC的第二区域在第一SiC层提供，具有第一导电类型和邻近于SiC的第一区域中。 设置在电压阻断SiC衬底的第二表面上具有第一导电类型的第二SiC层。 SiC的第三区域被设置在第二SiC层上，并具有第二导电类型。 SiC的第四区域在所述第二SiC层提供，具有第一导电类型和邻近于SiC的第三区域。 分别设置在SiC的第一和第三区域的第一和第二触点，。 因此，提供一种制造高压SiC器件的相关方法。

公开(公告)号：EP1882273A2

公开(公告)日：2008-01-30

申请号：EP06750425.8

申请日：2006-04-18

申请人： CREE, INC.

发明人： RYU, Sei-Hyung ,  JENNY, Jason R. ,  DAS, Mrinal K. ,  HOBGOOD, Hudson McDonald ,  AGARWAL, Anant K. ,  PALMOUR, John W.

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/24 ,  H01L21/04

CPC分类号： H01L29/7395 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66333

摘要： Silicon carbide high voltage semiconductor devices and methods of fabricating such devices are provided. The devices include a voltage blocking substrate. Insulated gate bipolar transistors are provided that have a voltage blocking substrate. Planar and beveled edge termination may be provided.

公开(公告)号：EP1876638A2

公开(公告)日：2008-01-09

申请号：EP07013139.6

申请日：2007-07-04

申请人： Nissan Motor Company, Ltd.

发明人： Hayashi, Tetsuya ,  Hoshi, Masakatsu ,  Shimoida, Yoshio ,  Tanaka, Hideaki ,  Yamagami, Shigeharu

IPC分类号： H01L21/04 ,  H01L21/331 ,  H01L29/267 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78 ,  H01L29/24

CPC分类号： H01L29/7828 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66068

摘要： A semiconductor substrate (1,2) made of a semiconductor material is prepared, and a hetero semiconductor region (3) is formed on the semiconductor substrate (1,2) to form a heterojunction in an interface between the hetero semiconductor region (3) and the semiconductor substrate (1,2). The hetero semiconductor region (3) is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region (3) includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region (3) with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film (4) adjacent to the heterojunction is formed. A gate electrode (5) is formed on the gate insulating film (4). This makes it possible to manufacture a semiconductor device including the gate insulating film (4) with a lower ON resistance, and with a higher insulating characteristic and reliability.

摘要翻译： 制备由半导体材料制成的半导体衬底（1,2），并且在半导体衬底（1,2）上形成异质半导体区域（3），以在异质半导体区域（3）之间的界面形成异质结， 和半导体衬底（1,2）。 异质半导体区域（3）由具有与半导体材料的带隙不同的带隙的半导体材料制成，并且异质半导体区域（3）的一部分包括膜厚度比膜厚度薄的膜厚控制部 其他部分。 通过以与膜厚控制部的膜厚相等的厚度氧化异质半导体区域（3），形成与异质结相邻的栅极绝缘膜（4）。 栅极电极（5）形成在栅极绝缘膜（4）上。 这使得可以制造包括具有较低导通电阻的栅极绝缘膜（4）并且具有更高绝缘特性和可靠性的半导体器件。

公开(公告)号：EP1872406A2

公开(公告)日：2008-01-02

申请号：EP06750118.9

申请日：2006-04-14

申请人： Southwall Technologies, Inc.

发明人： HOOD, Thomas, G. ,  WESTRA, Sicco, W.T.

IPC分类号： H01L29/24

CPC分类号： B32B17/10018 ,  B32B17/10174

摘要： Conductive micro traces (64) are formed on a coated or uncoated substrate (28) in order to achieve a combination of target optical properties and target electrical capabilities. For the coated substrate, the coating (100) may be formed before or after the conductive micro traces. Thecoating may be designed for providing IR filtering or reductions in reflected light and color shift, while the conductive micro traces may be used for EMI shielding or to provide current-carrying capability, such as when used as heaters. In another embodiment, the conductive micro traces are formed on an uncoated flexible transparent substrate and have a width of less than 25 microns, such that the conductive micro traces are capable of achieving their intended purpose while maintaining a high visible light transmissivity. The conductive micro traces may be formed using various approaches, such as the use of electroplating techniques or the use of inkjet printing techniques.

公开(公告)号：EP1872405A2

公开(公告)日：2008-01-02

申请号：EP06749000.3

申请日：2006-03-31

申请人： CARNEGIE MELLON UNIVERSITY

发明人： MCCULLOUGH, Richard, D. ,  IOVU, Mihaela, C. ,  SHEINA, Elena, E.

IPC分类号： H01L29/24

CPC分类号： C08G61/126 ,  B01J31/2409 ,  B01J2231/4205 ,  B01J2531/847 ,  H01L51/0036 ,  H01L51/0043

摘要： Regioregular poly(3-alkylthiophenes) and other polythiophenes can be prepared by living polymerization which have good solubility, processability and environmental stability. The polymerization method can afford regioregular poly(3-alkylthiophenes) in high yields. Kinetic study of polymerization revealed the living character of this process. The molecular weight of ρoly(3-alkylthiophenes) is a function of the molar ratio of the monomer to nickel initiator, and conducting polymers with relatively narrow molecular weight distribution (PDKl.5) are now readily available. Sequential monomer addition resulted in new block copolymers containing different poly(3-alkylthiophene) segments, which further confirms the 'livingness' of this system. Other synthetic methods can be used as well to conduct living polymerization. Blends and electronic devices can be prepared.

公开(公告)号：EP1852895A1

公开(公告)日：2007-11-07

申请号：EP06290725.8

申请日：2006-05-05

申请人： Kinik Company

发明人： Chang, Hsiao-Kuo ,  Huang, Jen-Sheuan ,  Chen, Chih-Peng ,  Chen, Na-Ling ,  Wen, Shih-Pang

IPC分类号： H01L21/20 ,  H01L29/24

CPC分类号： H01L21/02527 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0254 ,  H01L21/02664

摘要： A diamond substrate and a method for fabricating the same are provided wherein a SiC layer is formed on a lower surface of a diamond layer for preventing the diamond layer from being deformed after the process of forming the diamond substrate, and then a semiconductor layer is formed on the diamond layer or directly formed on the surface of the SiC layer. Thereby, the lattice mismatch between the diamond film layer and the semiconductor layer is mitigated by the SiC layer, and the crystalline quality of the semiconductor layer is improved, the fabricating process of the diamond substrate is simplified, and the performance and stability are enhanced.

摘要翻译： 提供一种金刚石基板及其制造方法，其中在金刚石层的下表面上形成SiC层，以防止金刚石层在形成金刚石基板的过程之后变形，然后形成半导体层 在金刚石层上或直接形成在SiC层的表面上。 因此，通过SiC层减轻了金刚石膜层和半导体层之间的晶格失配，提高了半导体层的结晶质量，简化了金刚石基板的制造工艺，提高了性能和稳定性。

公开(公告)号：EP1850396A2

公开(公告)日：2007-10-31

申请号：EP07008566.7

申请日：2007-04-26

申请人： NISSAN MOTOR CO., LTD.

发明人： Yamagami, Shigeharu ,  Hoshi, Masakatsu ,  Shimoida, Yoshio ,  Hayashi, Tetsuya ,  Tanaka, Hideaki

IPC分类号： H01L29/861 ,  H01L29/267 ,  H01L21/04 ,  H01L29/24

CPC分类号： H01L29/8613 ,  H01L21/0465 ,  H01L21/0475 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/6606 ,  H01L29/66136

摘要： As semiconductor regions in contact with a first main surface of a semiconductor base composed by forming an N- silicon carbide epitaxial layer on an N+ silicon carbide substrate connected to a cathode electrode, there are provided both an N+ polycrystalline silicon layer of a same conduction type as a conduction type of the semiconductor base and a P+ polycrystalline silicon layer of a conduction type different from the conduction type of the semiconductor base. Both the N+ polycrystalline silicon layer and the P+ polycrystalline silicon layer form a heterojunction with the semiconductor base, and are ohmically connected to the anode electrode. Moreover, the N+ polycrystalline silicon layer of the same conduction type as the conduction type of the semiconductor base is formed so as to contact the first main surface of the semiconductor base, and the P+ polycrystalline silicon layer of the conduction type different from the conduction type of the semiconductor base is formed in trenches dug on the first main surface of the semiconductor base.

摘要翻译： 作为通过在连接到阴极的N +碳化硅衬底上形成N-碳化硅外延层构成的半导体基底的第一主表面接触的半导体区域，提供了具有相同导电类型的N +多晶硅层 作为半导体基体的导电类型和与半导体基体的导电类型不同的导电类型的P +多晶硅层。 N +多晶硅层和P +多晶硅层都与半导体基底形成异质结，并且与欧姆电极连接。 此外，形成与半导体基体的导电类型相同的导电类型的N +多晶硅层，以便接触半导体基体的第一主表面和与导电类型不同的导电类型的P +多晶硅层 在半导体基底的第一主表面上挖出的沟槽中形成半导体基底。

公开(公告)号：EP1547131A4

公开(公告)日：2007-10-10

申请号：EP03736307

申请日：2003-06-30

申请人： MITSUI SHIPBUILDING ENG

发明人： NISHINO SHIGEHIRO ,  MURATA K

IPC分类号： C23C16/32 ,  C30B23/00 ,  H01L21/02 ,  H01L21/04 ,  H01L25/00 ,  H01L29/06 ,  H01L29/24 ,  C03B29/06 ,  C30B29/36 ,  H01L21/205

CPC分类号： C30B29/36 ,  C30B33/06 ,  H01L21/0445 ,  H01L29/0657 ,  H01L29/1608

摘要： From the viewpoint of manufacturing an SiC semiconductor device economically, a present Si device manufacturing line is utilized to make it possible to handle a small-diameter SiC wafer. Polycrystal SiC is grown from at least one surface side of a small-diameter a-SiC single crystal wafer so as to be in a size of an outer diameter corresponding to a handling device of an existing semiconductor manufacturing line, and thereafter the polycrystal SiC on the surface of the α-SiC single crystal wafer is ground to manufacture an increased-diameter SiC of a double structure in which the polycrystal SiC is grown around an outer circumference of the small-diameter α-SiC single crystal wafer.

公开(公告)号：EP1396890A4

公开(公告)日：2007-10-10

申请号：EP02736054

申请日：2002-06-11

申请人： SUMITOMO ELECTRIC INDUSTRIES

发明人： HARADA SHIN ,  HIROTSU KENICHI ,  MATSUNAMI HIROYUKI ,  KIMOTO TSUNENOBU

IPC分类号： H01L29/808 ,  H01L21/337 ,  H01L29/06 ,  H01L29/10 ,  H01L29/24 ,  H01L29/772

CPC分类号： H01L29/808 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/1608

摘要： The basic structure of this lateral JFET comprises an n type semiconductor layer (3) consisting of an n type impurity area, and a p type semiconductor layer consisting of a p type impurity area and formed on this n type semiconductor layer (3). In addition, provided in this p type semiconductor layer are a p+ type gate area layer (7) extending up to the n type semiconductor layer (3) and containing a p type impurity concentration higher than that of the n type semiconductor layer (3), and an n+ type drain area layer (9) positioned a specified distance apart from the p+ type gate area layer (7) and containing an n type impurity concentration higher than that of the n type semiconductor layer (3). This arrangement can provide a lateral JFET capable of retaining a high withstand voltage performance and reducing an on−resistance.

公开(公告)号：EP1102327B1

公开(公告)日：2007-10-03

申请号：EP00124837.6

申请日：2000-11-14

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

发明人： Takagi, Takeshi ,  Inoue, Akira

IPC分类号： H01L29/78 ,  H01L21/335 ,  H01L29/10 ,  H01L29/24 ,  H01L29/778 ,  H01L29/786

CPC分类号： H01L29/1054 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7782 ,  H01L29/783 ,  H01L29/78615 ,  H01L29/78648 ,  H01L29/78687