公开(公告)号：EP0596864A2

公开(公告)日：1994-05-11

申请号：EP94100767.6

申请日：1989-06-16

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Proebsting, Robert J.

IPC分类号： H03K19/017 ,  H03K5/153

CPC分类号： H03K19/01707 ,  G11C8/06 ,  G11C8/18 ,  H03K5/1504 ,  H03K5/1534 ,  H03K19/01721 ,  H03K19/018521

摘要： A speed enhancement technique for CMOS circuits is disclosed. In the series of logic stages, nodes in the signal path of a pulse are set by preceding logic stages, then reset by feedback from a subsequent logic stage. This eliminates the capacitive burden of resetting any given node from the input signal to allow substantially all of the input signal to be employed in setting the nodes to an active state rather than wasting half the signal in turning off the reset path. The technique is illustrated as applied to RAM circuits.

摘要翻译： 公开了一种用于CMOS电路的速度增强技术。 在一系列逻辑级中，脉冲信号路径中的节点由先前的逻辑级设置，然后通过后续逻辑级的反馈进行复位。 这消除了从输入信号复位任何给定节点的电容性负担，以允许基本上将所有输入信号用于将节点设置为活动状态，而不是在关闭复位路径时浪费信号的一半。 该技术被应用于RAM电路。

公开(公告)号：EP0596652A1

公开(公告)日：1994-05-11

申请号：EP93308572.2

申请日：1993-10-27

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Edem, Brian C. ,  Worsley, Debra J.

IPC分类号： H04L12/64 ,  H04L12/44 ,  H04J3/06

CPC分类号： H04L12/44 ,  H04L12/6418 ,  H04L2012/6427 ,  H04L2012/6437 ,  H04L2012/644 ,  H04L2012/6448 ,  H04L2012/6459

摘要： A data communication system, such as a local area network, is provided with a capability of transmitting isochronous data. Preferably the system conveys both isochronous data and non-isochronous data by time-multiplexing the data into a recurring frame structure on a four-bit nibble basis. Bandwidth available for a particular isochronous source/sink is selectable and sustainable with a predefined granularity. Data rates can be adjusted by using "rate adjustment" time slots which can transmit data in some frames and "no data" in other frames. A particular time frame or template is provided which accommodates isochronous data, non-isochronous data, D channel data, maintenance data and frame synchronization signals. Non-isochronous operation and bandwidth allocation is independent and transparent to the isochronous data activity. Frame timing can be coordinated with one or more reference clock signals, e.g., from a public telephone or wide area network. A buffer can convert between the source/sink or hub circuitry data rates and the data rates for transmission over the physical media which, for a given type of data, is discontinuous on a small time scale.

摘要翻译： 诸如局域网的数据通信系统被提供有传输等时数据的能力。 优选地，系统通过以四位半字节的方式将数据进行时分复用为循环帧结构来传送同步数据和非等时数据。 可用于特定等时源/宿的带宽可以预定义的粒度来选择和持续。 可以通过使用“速率调整”时隙来调整数据速率，这些时隙可以在某些帧中传输数据，而在其他帧中可以传送“无数据”。 提供了一个特定的时间框架或模板，它容纳同步数据，非等时数据，D信道数据，维护数据和帧同步信号。 非同步操作和带宽分配对于同步数据活动是独立且透明的。 帧定时可以与一个或多个参考时钟信号协调，例如来自公共电话或广域网。 缓冲器可以在源/汇或集线器电路数据速率和数据速率之间进行转换，以便通过物理介质进行传输，对于给定类型的数据，它们在小时间尺度上是不连续的。

公开(公告)号：EP0590818A3

公开(公告)日：1994-05-11

申请号：EP93307191.2

申请日：1993-09-13

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Sinh, Nguyen ,  Yee, Loren

IPC分类号： H03K19/0175

CPC分类号： H03K19/017527

摘要： An ECL-to-BiCMOS/CMOS translator for translating a pair of differential ECL level signals into a BiCMOS/CMOS level signal is disclosed. The translator includes an output stage (42) having an output node (50) and a first output switching means (Q13) for coupling the output node (50) to a first voltage (-V DD ) supply and a second output switching means (Q14) for coupling the output node (50) to a second voltage supply (V SS ). A first input stage (38) activates the first output switching means (Q13) of the output stage (42) in response to one of the differential ECL signals, and a second input stage (40) activates the second output switching means (Q14) of the output stage (42) in response to the other differential ECL signal. The first input stage (38) includes a first input switching means (MP6) for coupling a first resistive element (R12) between the first voltage supply (-V DD ) and the output node (50) of the output stage (42), and the second input stage (40) includes a second input switching means (MP8) for coupling a second resistive element (R14) between the first voltage supply (V DD ) and the second voltage supply (V SS ).

摘要翻译： 公开了用于将一对差分ECL电平信号转换成BiCMOS / CMOS电平信号的ECL到BiCMOS / CMOS转换器。 该转换器包括具有输出节点（50）和用于将输出节点（50）耦合到第一电压（-VDD）电源的第一输出开关装置（Q13）的输出级（42）和第二输出开关装置 ），用于将输出节点（50）耦合到第二电压源（VSS）。 响应于一个差动ECL信号，第一输入级（38）激活输出级（42）的第一输出开关装置（Q13），并且第二输入级（40）激活第二输出开关装置（Q14） 响应于另一个差分ECL信号，输出级（42）的输出信号。 第一输入级（38）包括用于耦合第一电压源（-VDD）和输出级（42）的输出节点（50）之间的第一电阻元件（R12）的第一输入开关装置（MP6），以及 第二输入级（40）包括用于耦合第一电压源（VDD）和第二电压源（VSS）之间的第二电阻元件（R14）的第二输入开关装置（MP8）。

公开(公告)号：EP0460440A3

公开(公告)日：1994-05-11

申请号：EP91108017.4

申请日：1991-05-17

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Aronowitz, Sheldon ,  Hart, Courtney L. ,  Buynoski, Matthew

IPC分类号： H01L21/266 ,  H01L21/76 ,  H01L21/316

CPC分类号： H01L21/02238 ,  H01L21/02299 ,  H01L21/266 ,  H01L21/31662 ,  H01L21/74 ,  Y10S438/945 ,  Y10S438/95 ,  Y10S438/966

摘要： A self-aligned masking process for use with ultra-high energy implants (implant energies equal to or greater than 1 MeV) is provided. The process can be applied to an arbitrary range of implant energies. Consequently, high doses of dopant may be implanted to give high concentrations that are deeply buried. This can be coupled with the fact that amorphization of the substrate lattice is relatively localized to the region where the ultra-high energy implant has peaked to yield a procedure to form buried, localized isolation structures.

公开(公告)号：EP0590827A2

公开(公告)日：1994-04-06

申请号：EP93307242.3

申请日：1993-09-14

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Rapp, Karl A.

IPC分类号： G11C5/14 ,  G11C16/06 ,  H02M3/07

CPC分类号： G11C5/145 ,  H02M3/073 ,  H02M2003/076

摘要： A charge pump for increasing the amplitude of a voltage supply signal is disclosed. The charge pump includes an auxiliary pump, a buffer stage, and a main pump. The auxiliary pump generates several intermediate voltage signals in response to a pair of complementary clock signals. Each intermediate voltage signal has a different amplitude which is greater than the amplitude of the voltage supply signal. The buffer stage increases the amplitudes of the pair of complementary clock signals in response to the several intermediate voltage signals generated by the auxiliary pump. The main pump increases the amplitude of the voltage supply signal in response to the pair of increased amplitude complementary clock signals generated by the buffer stage.

摘要翻译： 公开了一种用于增加电压信号的幅度的电荷泵。 电荷泵包括辅助泵，缓冲级和主泵。 辅助泵响应于一对互补时钟信号产生几个中间电压信号。 每个中间电压信号具有不同于电压信号幅度的幅度。 响应于由辅助泵产生的几个中间电压信号，缓冲级增加该对互补时钟信号的幅度。 响应于由缓冲器级产生的一对增加的幅度互补时钟信号，主泵增加电压信号的幅度。

公开(公告)号：EP0587265A1

公开(公告)日：1994-03-16

申请号：EP93302343.4

申请日：1993-03-26

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Wile, Donald T.

IPC分类号： H03F3/45 ,  H03F1/32

CPC分类号： H03F3/4517 ,  H03F1/3211 ,  H03F3/45085 ,  H03F2203/45018 ,  H03F2203/45032 ,  H03F2203/45094 ,  H03F2203/45188 ,  H03F2203/45318 ,  H03F2203/45346 ,  H03F2203/45352 ,  H03F2203/45664 ,  H03F2203/45674 ,  H03F2203/45722

摘要： A monolithic silicon, planar epitaxial, PN junction isolated integrated circuit employing an input stage for an operational amplifier in which the input stage displays reduced transconductance. This provides a means for reducing the size of the amplifier compensation capacitor which typically requires the most chip area of any circuit component. The transconductance reduction is achieved by forming the input stage from ratioed plural collector lateral transistors (15,16) which drive a current mirror load (17). The plural collectors are cross-coupled to the current mirror load and the collector ratio determines the transconductance reduction.

摘要翻译： 采用输入级用于运算放大器的单片硅平面外延PN结隔离集成电路，其中输入级显示减少的跨导。 这提供了用于减小放大器补偿电容器的尺寸的手段，其通常需要任何电路部件的最大芯片面积。 通过从驱动电流镜载荷（17）的比例多个集电极横向晶体管（15,16）形成输入级来实现跨导减少。 多个集电极交叉耦合到电流反射镜负载，并且集电极比决定了跨导降低。

公开(公告)号：EP0587212A2

公开(公告)日：1994-03-16

申请号：EP93202353.4

申请日：1993-08-10

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Hoang, Tuong Hai ,  Izadinia, Mansour

IPC分类号： H01L27/02 ,  H02H9/04

CPC分类号： H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit utilizable for protecting an integrated circuit feature from electrostatic discharge is disclosed. A first bipolar transistor (Q10) has its emitter connected to the IC feature and its collector connected to ground. A second bipolar transistor (Q20) has its emitter connected to the IC feature and its collector connected to its base and to the base of the first bipolar transistor. A field effect transistor (M10) has its gate and drain connected to the IC feature and its body connected to its source and to the collector and base of the second bipolar transistor and to the base of the first bipolar transistor. A diode (D10) has its cathode connected to the body and the source of the field effect transistor and to the collector and base of the second bipolar transistor and to the base of the first bipolar transistor.

摘要翻译： 可利用用于保护集成电路特征免受静电放电的电路是游离缺失盘。 第一双极晶体管（Q10）的发射极连接到接地的IC功能和它的集电极。 第二双极晶体管（Q20）的发射极连接到与它的基和所述第一双极晶体管的基极的集成电路特征和它的集电极。 一种场效应晶体管（M10）的栅极和漏极连接到连接到它的源极和到所述第二双极型晶体管的集电极和基极和到所述第一双极晶体管的基极的集成电路特征和它的身体。 二极管（D10）的阴极连接到所述主体和所述场效应晶体管的源极和到所述第二双极型晶体管的集电极和基极和到所述第一双极晶体管的基极。

公开(公告)号：EP0293798B1

公开(公告)日：1994-02-23

申请号：EP88108605.2

申请日：1988-05-30

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Evans, Joseph T., Jr. ,  Miller, William D. ,  Womack, Richard H.

IPC分类号： G11C11/22 ,  G11C11/56 ,  G11C17/04

CPC分类号： G11C11/22 ,  G11C11/5657

公开(公告)号：EP0582365A1

公开(公告)日：1994-02-09

申请号：EP93302344.2

申请日：1993-03-26

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Wile, Donald T.

IPC分类号： G06G7/24

CPC分类号： G06G7/24

摘要： A dual input differential signal summer combines a pair of differential input signals logarithmically to produce a differential output. The input signals are applied to a pair of differential amplifiers the outputs of which are buffered so that they do not interact. The result is an increased circuit transconductance. Where the circuit is employed in a tunable filter integrated circuit employing plural cascade filter elements a substantial reduction in chip power is achieved.

摘要翻译： 双输入差分信号加法器将一对差分输入信号对数地组合以产生差分输出。 输入信号被施加到一对差分放大器，其输出被缓冲使得它们不相互作用。 结果是增加的电路跨导。 在采用多级联滤波器元件的可调谐滤波器集成电路中采用电路的情况下，实现了芯片功率的显着降低。

公开(公告)号：EP0549165A3

公开(公告)日：1994-01-05

申请号：EP92311063.9

申请日：1992-12-03

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： Utz, Hubert

IPC分类号： H03K17/94 ,  H03K17/28 ,  H03K19/00 ,  G06F1/32

CPC分类号： G06F1/3228 ,  H03K17/28 ,  H03K17/94 ,  H03K19/0016 ,  H03K2217/0036

摘要： A power conserving integrated circuit (20) is coupled to its external power supply (28) only in response to an external event sensed by closure of a switch (30). An initial power connection is made by a transistor (34) in the circuit (22) in response to the external event. After the initial power connection, the transistor (34) remains conducting so as to couple the power supply (28) to the integrated circuit (22) for a predetermined period of time sufficient for a function (40) to be executed by the integrated circuit. The initial power connection is detected by an activity monitor (37) which in response resets a down counter (38) that, through a connection (39) to the transistor (34), holds the transistor (34) in its conducting state until the counter (38) finishes counting clock pulses. The connection is then terminated and is not re-initiated until another external event. Therefore, power is consumed only when necessary, thereby preserving the power source (28).

摘要翻译： 节能集成电路（20）仅响应于通过闭合开关（30）而感测到的外部事件而耦合到其外部电源（28）。 响应于外部事件，由电路（22）中的晶体管（34）进行初始功率连接。 在初始电源连接之后，晶体管（34）保持导通，从而将电源（28）耦合到集成电路（22）预定的时间段，足以使功能（40）由集成电路 。 初始电源连接由活动监控器（37）检测，活动监控器（37）作为响应重新设置下降计数器（38），通过与晶体管（34）的连接（39）将晶体管（34）保持在其导通状态，直到 计数器（38）完成对时钟脉冲的计数。 该连接然后被终止，直到另一个外部事件才被重新启动。 因此，仅在必要时才消耗电力，从而保留电源（28）。