Terrestrial-digital multimedia broadcasting receiver
    12.
    发明公开
    Terrestrial-digital multimedia broadcasting receiver 审中-公开
    地面数字多媒体广播接收器

    公开(公告)号:EP1868308A3

    公开(公告)日:2011-01-26

    申请号:EP07108862.9

    申请日:2007-05-24

    IPC分类号: H04H1/00

    摘要: Provided is a terrestrial-digital multimedia broadcasting (T-DMB) receiver. A T-DMB receiver comprises a low noise amplifier amplifying a radio frequency (RF) signal for T-DMB, a down-conversion mixer directly down converting the RF signal amplified at the low noise amplifier into a baseband signal, a down frequency oscillator generating a frequency for the down-conversion and supplying the frequency to the down-conversion mixer, and a filtering unit filtering the baseband signal output from the down-conversion mixer.

    Double conversion receiver
    15.
    发明公开
    Double conversion receiver 审中-公开
    Doppelüberlagerungsempfänger

    公开(公告)号:EP1845625A2

    公开(公告)日:2007-10-17

    申请号:EP07105547.9

    申请日:2007-04-03

    IPC分类号: H04B1/26

    摘要: Provided is a double conversion receiver. The double conversion receiver comprises a direct down-converter down converting a radio frequency (RF) signal at a RF band into a zero-intermediate frequency (IF) signal at a zero-IF band, and an intermediate up-converter up converting the down-converted zero-IF signal into a low-IF signal at a low-IF band.

    摘要翻译: 提供了双转换接收机。 双转换接收机包括直接下变频器将RF频带处的射频(RF)信号转换成零中频频带的零中频(IF)信号,以及中间上变频器向上转换下变频 将低中频信号转换为低IF频带的低中频信号。

    Adaptive linear amplifier
    16.
    发明公开
    Adaptive linear amplifier 审中-公开
    Adaptitor linearerVerstärker

    公开(公告)号:EP1833161A1

    公开(公告)日:2007-09-12

    申请号:EP07103382.3

    申请日:2007-03-02

    IPC分类号: H03F1/32 H03F3/21

    CPC分类号: H03F1/301 H03F3/193 H03F3/68

    摘要: The present invention relates to an amplifier and, more particularly, to an adaptive linear amplifier (200) with low power consumption and a high linearity. The adaptive linear amplifier (200) according to the present invention comprises amplification means (210) and a bias controller (230). The amplification means (210) comprises a main transistor (MN 21 ) and an auxiliary transistor unit (211). The main transistor (MN 21 ) and the auxiliary transistor unit (211) are coupled to each other. The bias controller (230) controls a bias Voltage applied to the main transistor (MN 21 ) and the auxiliary transistor unit (211).

    摘要翻译: 本发明涉及放大器,更具体地,涉及一种具有低功耗和高线性度的自适应线性放大器(200)。 根据本发明的自适应线性放大器(200)包括放大装置(210)和偏置控制器(230)。 放大装置(210)包括主晶体管(MN 21)和辅助晶体管单元(211)。 主晶体管(MN 21)和辅助晶体管单元(211)彼此耦合。 偏置控制器(230)控制施加到主晶体管(MN 21)和辅助晶体管单元(211)的偏置电压。

    Differential amplifier circuit and mixer circuit having improved linearity
    17.
    发明公开
    Differential amplifier circuit and mixer circuit having improved linearity 审中-公开
    差分放大器电路和混频器电路具有改进的线性度

    公开(公告)号:EP1622260A3

    公开(公告)日:2007-01-03

    申请号:EP05016435.9

    申请日:2005-07-28

    IPC分类号: H03F3/45

    摘要: The present invention relates to a differential amplifier and a mixer for improving the linearity. The differential amplifier circuit according to this present invention, includes first and second load stages each having a predetermined voltage value, a main differential amplifier unit having a first differential stage that forms a differential pair in such a way as to amplify a difference between a first input voltage and a second input voltage, and a constant current source, which has a predetermined current driving capability and is connected serially between a power source voltage terminal and a ground terminal, and a auxiliary differential amplifier unit having a second differential stage that forms a differential pair in such a way as to amplify a difference between a third input voltage and a fourth input voltage connected between the first load stage and a second load stage, and the ground, respectively.

    Active circuit having improved linearity using common gate transistors
    19.
    发明公开
    Active circuit having improved linearity using common gate transistors 审中-公开
    Aktive Schaltung mit verbesserterLinearitätmittels Transistoren in Gateschaltung

    公开(公告)号:EP1633041A2

    公开(公告)日:2006-03-08

    申请号:EP05108170.1

    申请日:2005-09-06

    IPC分类号: H03F1/32 H03F3/345

    摘要: The present invention relates to improved linearity of an active circuit, and more particularly, to an active circuit having improved linearity using a main circuit unit (301) and an assistant circuit unit (302). According to the present invention, the common gate circuit includes a main circuit unit (301) consisting of a common gate circuit having a drain terminal through which an input signal (IN) is output as an output signal, an assistant circuit unit (302) having a common gate circuit in order to assist the linearity of the main circuit unit (301), a biasing unit (biasing circuit) for biasing the main circuit unit (301) and the assistant circuit unit (302), respectively, and load stages (load impedance) connected to output stages of the main circuit unit (301) and the assistant circuit unit (302), wherein the output stages of the main circuit unit and the assistant circuit unit are coupled to each other.

    摘要翻译: 本发明涉及有源电路的改进的线性度,更具体地说,涉及使用主电路单元(301)和辅助电路单元(302)具有改进的线性度的有源电路。 根据本发明,公共门电路包括:主电路单元(301),具有通过输入信号(IN)作为输出信号的漏极端子的公共栅极电路,辅助电路单元(302) 具有公共门电路以辅助主电路单元(301)的线性度,分别用于偏置主电路单元(301)和辅助电路单元(302)的偏置单元(偏置电路)和负载级 (负载阻抗)连接到主电路单元(301)和辅助电路单元(302)的输出级,其中主电路单元和辅助电路单元的输出级彼此耦合。

    DVB-H receiver chip employing diversity scheme
    20.
    发明公开
    DVB-H receiver chip employing diversity scheme 审中-公开
    DVB-H接收器芯片分集方案

    公开(公告)号:EP1876718A3

    公开(公告)日:2011-04-13

    申请号:EP07109753.9

    申请日:2007-06-06

    IPC分类号: H04B1/08 H04B1/26

    CPC分类号: H04B1/30 H04B7/08 H04B7/0831

    摘要: The present invention relates to a receiver chip used in a Digital Video Broadcasting (DVB) receiver, and more particularly, to a Digital Video Broadcasting-Handheld (DVB-H) receiver chip employing a diversity scheme. In the DVB-H receiver chip according to the present invention, a first receiver block 101 and a second receiver block 102 isolated from the first receiver block are packaged within one receiver chip. An I/O terminal of the first receiver block 101 is connected to an external pin of one side 120 of the receiver chip, and an I/O terminal of the second receiver block 102 is connected to an external pin of a side 130 opposite to the one side 120 of the receiver chip. A source terminal or a control terminal of the first or second receiver block 101 or 102 is connected to the external pin of one or more of the one side 120 or the other sides 110 and 140 of the receiver chip. The first receiver block 101 comprises a first Low-Noise Amplifier (LNA) 311, a first mixer 312, a first filter 313 and a first a Variable Gain Amplifier (VGA) 314. The second receiver block 102 comprises a second LNA 321, a second mixer 322, a second filter 323 and a second VGA 324. A Voltage-Controlled Oscillator (VCO) supplies a frequency to the first and second mixers 312 and 322.