公开(公告)号：EP0015070A1

公开(公告)日：1980-09-03

申请号：EP80300235.1

申请日：1980-01-24

申请人： FUJITSU LIMITED

发明人： Yamauchi, Takahiko

IPC分类号： G11C7/06 ,  H03K5/02

CPC分类号： G11C11/419 ,  H03K19/01707

摘要： A sense amplifier circuit comprising of one or two differential amplifiers to each of which are connected one or two reference transistors (Q 15 , Q' 15 resp. Q 25 , Q' 25 ) for producing the reference voltages (V' R i resp. V' R2 ) of the corresponding differential amplifiers. The reference transistors are controlled by input signals (e.g. V i1 ) and/or output signals (e.g. V 02 ) of the differential amplifiers.

公开(公告)号：EP0090590B1

公开(公告)日：1987-03-04

申请号：EP83301616.5

申请日：1983-03-23

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko ,  Seki, Teruo Dai-2-Yayoi-so 5

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C8/00 ,  G11C8/18 ,  G11C11/419

公开(公告)号：EP0090632A3

公开(公告)日：1986-10-15

申请号：EP83301734

申请日：1983-03-28

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko ,  Seki, Teruo

IPC分类号： G11C11/40

CPC分类号： G11C11/419 ,  G11C11/418

摘要： A static-type RAM device in which the amplitude of the data signal stored in a memory cell just after the writing in of data is completed is increased and the stability of the data stored in each memory cell is increased. The RAM device comprises a bit-line pufling-up means for pulling up the potential of a bit line to a voltage which is approximately equal to or larger than the power supply voltage and a word-line pulling-up means for pulling up the potential of a selected word line to a voltage which is larger than the power supply voltage after the writing in of data is completed.

公开(公告)号：EP0054471A3

公开(公告)日：1984-07-18

申请号：EP81401930

申请日：1981-12-04

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko

IPC分类号： H01L29/86 ,  H01L27/06 ,  H01L29/78 ,  G11C11/40

CPC分类号： H01L28/20 ,  G11C11/412 ,  H01L27/0688 ,  H01L27/1112 ,  H01L29/66992 ,  H01L29/8605

摘要： A semiconductor resistor element comprising a semiconductor film (14) which has a desired shape and electrode wirings (20a-20b) at both ends thereof, and a control electrode (18) provided between the two ends of the semiconductor film (14) via an insulating film (16). The control electrode (18) is served with a control voltage which controls the resistance of the semiconductor film. Namely, the control electrode is served with a control voltage that changes with the change in temperature to offset the change in resistance of the semiconductor film caused by the change in temperature.

公开(公告)号：EP0100166A2

公开(公告)日：1984-02-08

申请号：EP83303915.9

申请日：1983-07-05

申请人： FUJITSU LIMITED

发明人： Yamauchi, Takahiko ,  Seki, Teruo ,  Aoyama, Keizo

IPC分类号： H01L23/48

CPC分类号： H01L23/485 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： in a semiconductor device including a connection structure comprising a first conductive layer 14 formed in or on a semiconductor substrate 11, a second conductive layer 15 arranged adjacent the first conductive layer 14, and a third conductive layer 17 connecting the first conductive layer 14, and to the second conductive layer 15. The third conductive layer 17 is in contact with the first 14 and second 15 conductive layers in a contact region 16'. One dimension of the portion of the second conductive layer 15 in the contact region 16' varies which enables the size of the contact region 16' to be reduced whilst still ensuring a positive connection between the first 14 and second 15, conductive layers even in the event of their misregistry.

摘要翻译： 在包括形成在半导体衬底11中或其上的第一导电层14的连接结构的半导体器件中，邻近第一导电层14布置的第二导电层15和连接第一导电层14的第三导电层17和 到第二导电层15.第三导电层17在接触区域中与第一14和第二导电层16接触。 接触区域16分钟内的第二导电层15的一部分的一个尺寸变化，这使得接触区域16分钟的尺寸能够减小，同时仍然确保第一导电层14和第二导电层14之间的正连接，即使在 他们的错误事件。

公开(公告)号：EP0087979A2

公开(公告)日：1983-09-07

申请号：EP83301104.2

申请日：1983-03-02

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko ,  Seki, Teruo

IPC分类号： H01L27/10 ,  G11C11/40

CPC分类号： G11C5/063 ,  G11C5/005 ,  G11C5/14 ,  G11C11/4125 ,  H01L23/556 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/927 ,  H01L2924/00

摘要： A static-type semiconductor memory device having a three-layer structure; the gate-electrode wiring lines being formed by a first conductive layer of, for example, polycrystalline silicon; the word lines, the ground lines, and the power supply lines being formed by a second conductive layer of, for example, aluminum; and the bit lines being formed by a third conductive layer of, for example, aluminum; the bit lines extending in a column direction, and the ground lines extending in a row direction; whereby an improved integration degree, an improved operating speed, an improved manufacturing yield, and a countermeasure for soft errors due to alpha particles are attained.

摘要翻译： 一种具有三层结构的静态型半导体存储器件; 栅电极布线由例如多晶硅的第一导电层形成; 字线，地线和电源线由例如铝的第二导电层形成; 并且位线由例如铝的第三导电层形成; 位线沿列方向延伸，地线沿行方向延伸; 由此获得改进的集成度，改进的操作速度，改进的制造良率以及由α粒子引起的软误差的对策。

公开(公告)号：EP0083482A1

公开(公告)日：1983-07-13

申请号：EP82306641.0

申请日：1982-12-13

申请人： FUJITSU LIMITED

发明人： Seki, Teruo ,  Aoyama, Keizo ,  Yamauchi, Takahiko

IPC分类号： H03K19/017 ,  H03K19/094 ,  G11C8/00

CPC分类号： H03K19/09443 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/418 ,  H03K19/017

摘要： A logic circuit comprises a plurality of input terminals (IN 1 , IN 2 ,...), an output terminal (OUT), a load (L), and at least two driver circuits (D 1 , D 2 ,...). Each of the driver circuits (D 1 , D 2 ....) comprises a plurality of gates (Q l1 , Q l2 ,...) connected in series, each gate being driven by the potential at one of the input terminals (IN 1 , IN 2 ,...). In addition, first gates (Q 11 , Q 22 ,...) of the driver circuits (D 1 , D 2 ,...) connected directly to the output terminal (OUT) are driven by the potentials at different input terminals. With this arrangement at least one of the driver circuits (D 1 , D 2 ,...) operates rapidly in response to changes of input signals so as to change the potential at the output terminal (OUT). As a result, no fluctuation in operation speed is generated under any conditions of input signals, and, in addition, the operation speed is increased.

公开(公告)号：EP0055601A2

公开(公告)日：1982-07-07

申请号：EP81306073.8

申请日：1981-12-23

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko

IPC分类号： H03K19/017 ,  H03K5/02

CPC分类号： H03K19/017 ,  H03K5/023 ,  H03K19/01714

摘要： n a buffer circuit comprising a first, a second and a third transistor (31, 32, 33) and a capacitor (4) for bootstrap action, an inverter (52) is connected to the output point (6) at which the second and third transistors are connected in series, the inverter inverting the output signal (Sout) and supplying the inverted signal (S52) to the gate of the first transistor (31), thereby to increase the rate of rise of the leading edge of an output signal pulse.

摘要翻译： 该缓冲器电路包括用于自举动作的第一，第二和第三晶体管（31,32,33）和电容器（4），反相器（52）连接到输出点（6），在该输出点处第二和第三 晶体管串联连接，反相器将输出信号（Sout）反相并将反相信号（S52）提供给第一晶体管（31）的栅极，由此增加输出信号脉冲的前沿的上升率 。

公开(公告)号：EP0041844A2

公开(公告)日：1981-12-16

申请号：EP81302502.0

申请日：1981-06-05

申请人： FUJITSU LIMITED

发明人： Itoh, Hideo ,  Yamauchi, Takahiko

IPC分类号： H01L27/02 ,  G11C5/00

CPC分类号： G11C5/025 ,  G11C5/14 ,  H01L23/5286 ,  H01L24/06 ,  H01L27/0207 ,  H01L2224/05554 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor memory device has memory cells 2 and decoder circuitry 3 disposed centrally thereof. A ground line 7' extends around the memory cells 2 and the decoder circuitry 3. Control circuits 41 to 46 are disposed beneath or outwardly of the ground line 7'. Signal lines 5' for connecting the control circuits to one another are disposed outwardly of the control circuits41 to46. A power line 6' is inturn disposed outwardly of the signal lines 5'. This layout can provide for a reduction in the number of bridges required.

摘要翻译： 半导体存储器件具有设置在其中心的存储单元2和解码器电路3。 地线7分钟围绕存储器单元2和解码器电路3延伸。控制电路41至46设置在接地线下方或之外7分钟。 用于将控制电路彼此连接的信号线设置在控制电路41至46的外部。电源线6分钟依次设置在信号线5分钟之外。 这种布局可以减少所需的桥梁数量。

公开(公告)号：EP0090632B1

公开(公告)日：1989-07-19

申请号：EP83301734.6

申请日：1983-03-28

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko ,  Seki, Teruo

IPC分类号： G11C11/40

CPC分类号： G11C11/419 ,  G11C11/418