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21 条记录 (耗时 0.015 秒)

    Method of forming emitter and intrinsic base regions of a bipolar transistor
    11.
    发明公开
    Method of forming emitter and intrinsic base regions of a bipolar transistor 失效
    形成双极晶体管的发射极和内部基极区域的方法

    公开(公告)号：EP0090940A3

    公开(公告)日：1986-10-01

    申请号：EP83101761

    申请日：1983-02-23

    申请人： International Business Machines Corporation

    发明人： Barson, Fred ,  Kemlage, Bernard Michael

    IPC分类号： H01L21/225 ,  H01L21/285 ,  H01L21/82 ,  H01L29/10

    CPC分类号： H01L29/66272 ,  H01L21/2257 ,  H01L21/32155 ,  H01L29/1004 ,  H01L29/66287

    摘要： A method for fabricating high performance NPN bipolar transistors which result in shallow, narrow base devices is described. The method includes depositing a polycrystalline silicon layer (30) over a monocrystalline silicon surface in which the base and emitter regions (42, 44) of the transistor are to be formed. Boron ions (32) are ion implanted into the polycrystalline silicon layer (30) near the interface of the polycrystalline silicon layer with the monocrystalline silicon layer. An annealing of the layer structure partially drives in the boron into the monocrystalline silicon substrate. Arsenic ions (38) are ion implanted into the polycrystalline silicon layer (30). A second annealing step is utilized to fully drive in the boron to form the base region (42) and simultaneously therewith drive in the arsenic to form the emitter region (44) of the transistor. This process involving a two-step annealing process for the boron implanting ions is necessary to create a base with sufficient width and doping to avoid punch-through. There is also described a method for forming NPN transistors in an integrated circuit.

    Method of manufacturing a minimum bird's beak recessed oxide isolation structure
    12.
    发明公开
    Method of manufacturing a minimum bird's beak recessed oxide isolation structure 失效
    一种制造嵌入氧化物的绝缘结构以最小的鸟喙的方法。

    公开(公告)号：EP0111774A1

    公开(公告)日：1984-06-27

    申请号：EP83111758.5

    申请日：1983-11-24

    申请人： International Business Machines Corporation

    发明人： Fabricius, Karen Ann ,  Kemlage, Bernard Michael

    IPC分类号： H01L21/76 ,  H01L21/32

    CPC分类号： H01L21/76205 ,  H01L21/32

    摘要： A method for making a dielectric isolation pattern in integrated circuit structure is described. A monocrystalline silicon body (10, 20) is provided. There is formed thereon a layered structure (22, 24, 26) of silicon dioxide, polycrystalline silicon and silicon nitride, in that order. The layers are patterned to form openings in the structure at the areas where it is desired to form an oxide isolation pattern within the monocrystalline silicon body. If it is desired to form a semi-recessed oxide isolation there will be no etching of the monocrystalline silicon body in the openings. Should it be desired to form a full recessed oxide isolation there is etching of the monocrystalline silicon to a desired depth to form a substantially planar top surface of the monocrystalline with the recessed dielectric oxide isolation. The body is then oxidized until the desired oxide isolation pattern penetrates to the desired depth within the silicon body. Through a reduced silicon oxide layer (22) and by adding the polycrystalline silicon layer (24) a substantially reduced lateral oxidation and thus smaller beak length is achieved allowing higher integration density.

    Fabrication process for a shallow emitter, narrow intrinsic base transistor
    13.
    发明公开
    Fabrication process for a shallow emitter, narrow intrinsic base transistor 失效
    Verfahren zur Herstellung eines晶体管mit flachem发射器和schmalem intrinsischem Basisgebiet。

    公开(公告)号：EP0094482A2

    公开(公告)日：1983-11-23

    申请号：EP83102360.1

    申请日：1983-03-10

    申请人： International Business Machines Corporation

    发明人： Kemlage, Bernard Michael

    IPC分类号： H01L21/225 ,  H01L29/08 ,  H01L29/10 ,  H01L29/72

    CPC分类号： H01L29/1004 ,  H01L21/033 ,  H01L21/2257 ,  H01L29/7325 ,  Y10S438/92 ,  Y10S438/965

    摘要： A high performance bipolar transistor having a shallow emitter and a narrow intrinsic base region is fabricated by a minimum number of process steps. A silicon semiconductor body 10 is provided with regions of monocrystalline silicon isolated from one another by isolation regions (18) an epitaxial layer (14) and a buried subcollector (12). A layer (24) of polycrystalline silicon is deposited on the body. The surface of the polycrystalline silicon layer (24) is oxidized and the polycrystalline silicon is implanted with a base impurity. Silicon nitride and oxide layers (28, 30) are deposited on the polysilicon layer. An opening is made in the surface oxide layer (28) and the silicon nitride layer (30) to define the emitter area of the transistor. The polycrystalline silicon is thermally oxidized to drive the base impurity into the substrate. The thermal oxide is removed in an isotropic etch to leave an oxide sidewall cover (38) on the polycrystalline silicon. An emitter impurity is ion implanted into the polycrystalline silicon in the emitter area and then driven into the substrate. Collector, base and emitter contact openings are made and conductive metallurgy is formed.

    摘要翻译： 通过最少数量的工艺步骤制造具有浅发射极和窄本征基极区域的高性能双极晶体管。 硅半导体本体10设置有通过隔离区域（18），外延层（14）和掩埋子集电极（12）彼此隔离的单晶硅的区域。 多晶硅层（24）沉积在主体上。 多晶硅层（24）的表面被氧化并且多晶硅被注入碱性杂质。 氮化硅和氧化物层（28,30）沉积在多晶硅层上。 在表面氧化物层（28）和氮化硅层（30）中形成开口以限定晶体管的发射极区域。 多晶硅被热氧化以将基底杂质驱动到衬底中。 在各向同性蚀刻中去除热氧化物，以在多晶硅上留下氧化物侧壁盖（38）。 将发射极杂质离子注入到发射极区域中的多晶硅中，然后驱动到衬底中。 制成集电极，基极和发射极接触开口，形成导电冶金。

    Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits
    19.
    发明公开
    Integrated circuit structure and method for forming a recessed isolation structure for integrated circuits 失效
    集成电路装置和方法用于制造凹陷的隔离结构的用于集成电路。

    公开(公告)号：EP0073370A2

    公开(公告)日：1983-03-09

    申请号：EP82107225.3

    申请日：1982-08-10

    申请人： International Business Machines Corporation

    发明人： Joy, Richard Carleton ,  Kemlage, Bernard Michael ,  Mauer IV, John Lester

    IPC分类号： H01L21/76 ,  H01L21/74

    CPC分类号： H01L21/76202 ,  H01L21/743 ,  H01L21/763

    摘要： An integrated circuit structure having substrate contacts formed as a part of the isolation structure and method for making the same is described. The integrated circuit structure is composed of a monocrystalline silicon body (2, 4) having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion (22, 24) at and just below the surface of the integrated circuit and a deep portion which extends from the side of the recessed dielectric portion opposite to that portion at the surface of said body into the monocrystalline silicon body. A highly doped polycrystalline silicon substrate contact (20) is located within the deep portion of the pattern of isolation. At certain locations the deep portion of the pattern extends to the surface of the silicon body where interconnection metallurgy can electrically contact the polycrystalline silicon so as to form a substrate contact to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

    Mask for thermal oxidation and method of forming dielectric isolation surrounding regions
    20.
    发明公开
    Mask for thermal oxidation and method of forming dielectric isolation surrounding regions 失效
    Maske gegen thermische Oxydation und Verfahren zur Herstellung umringender dielektrischer Isolationszonen。

    公开(公告)号：EP0071203A2

    公开(公告)日：1983-02-09

    申请号：EP82106651.1

    申请日：1982-07-23

    申请人： International Business Machines Corporation

    发明人： Kemlage, Bernard Michael

    IPC分类号： H01L21/32 ,  H01L21/314 ,  H01L21/76

    CPC分类号： H01L21/76213 ,  H01L21/3145 ,  H01L21/32 ,  H01L21/7621

    摘要： The invention relates to a mask for thermal oxidation and a method for forming dielectric isolation surrounding regions.
    A mask and a method for eliminating "bird's head and beak" in recessed oxide isolation are described. The ROI mask uses a silicon oxynitride layer confronting the substrate with a silicon nitride layer convering the silicon oxynitride layer.

    摘要翻译： 用于在衬底中形成凹陷氧化物隔离的掩模包括在衬底上具有氧化硅层的叠层和在氮氧化硅上的氮化硅层。 通过（a）在Si上沉积Si氮氧化物层来形成晶体Si周围区域的介电隔离区; （b）在Si氮氧化物上沉积氮化硅层; （c）在要形成绝缘隔离区的氮化硅和氧氮化物中形成开口; （d）使用这些层作为掩模蚀刻Si衬底中的沟槽; 和（e）在开口中热氧化Si以形成SiO 2的介电隔离区，其中Si氧氮化物用作氧化屏障。 的Si表面。 县。 Si氮氧化物的折射率为1.65-1.90，特别是 1.70。 “鸟喙”被消除，提高了包装密度，而“鸟头”降低到可接受的水平，允许在隔离区域的周围形成堆叠的通孔。 拉伸应力最小化，避免了缺陷的任何增加，保持了高产量。