公开(公告)号：EP2419933A2

公开(公告)日：2012-02-22

申请号：EP10765114.3

申请日：2010-04-14

申请人： QUALCOMM Incorporated

发明人： ZHU, Xiaochun ,  NOWAK, Matthew ,  LI, Xia ,  KANG, Seung H.

IPC分类号： H01L27/115 ,  G11C11/15 ,  G11B5/39

CPC分类号： H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3254 ,  H01F10/3272 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.

公开(公告)号：EP2404302A1

公开(公告)日：2012-01-11

申请号：EP10707194.6

申请日：2010-03-04

申请人： QUALCOMM Incorporated

发明人： LI, Xia ,  NOWAK, Matthew ,  KANG, Seung, H. ,  HENDERSON, Brian, Matthew

IPC分类号： H01F17/00 ,  H01F41/04 ,  H01F41/34 ,  H01L23/522

摘要： An integrated magnetic film enhanced inductor and a method of forming an integrated magnetic film enhanced inductor are disclosed. The integrated magnetic film enhanced inductor includes an inductor metal having a first portion and a second portion, a top metal or bottom metal coupled to the inductor metal, and an isolation film disposed one of in, on, and adjacent to at least one of the first portion and the second portion of the inductor metal. The isolation film includes a magnetic material, such as a magnetic film.

公开(公告)号：EP2335282A1

公开(公告)日：2011-06-22

申请号：EP09792137.3

申请日：2009-09-01

申请人： QUALCOMM Incorporated

发明人： KASKOUN, Kenneth ,  GU, Shiqun ,  NOWAK, Matthew

IPC分类号： H01L25/065 ,  H01L23/60 ,  H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/60 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01093 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.

摘要翻译： 静电放电（ESD）保护装置在堆叠的半导体这个从而利用空间做否则将被用于通信目的仅用于有源层之间的垂直空间制成。 的穿硅通孔（TSV）的垂直表面区域被用于吸收大量的电压从ESD事件导致的。 在一个，ESD二极管的实施方式中的堆叠装置的半导体管芯的有源层之间的垂直TSV被创建。 此ESD二极管可通过电路在堆叠的两个半导体裸片由此节省了空间并减少由ESD保护电路所需的面积被共享。

公开(公告)号：EP2304792A1

公开(公告)日：2011-04-06

申请号：EP09770821.8

申请日：2009-06-19

申请人： QUALCOMM Incorporated

发明人： GU, Shiqun ,  NOWAK, Matthew ,  TOMS, Thomas R.

IPC分类号： H01L25/065 ,  H01L23/38

摘要： Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.