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31 条记录 (耗时 0.016 秒)

    FLASH STORAGE SYSTEM WITH WRITE/ERASE ABORT DETECTION MECHANISM
    12.
    发明公开
    FLASH STORAGE SYSTEM WITH WRITE/ERASE ABORT DETECTION MECHANISM 有权
    具有写入闪存系统/删除取消检测机构

    公开(公告)号：EP1700312A1

    公开(公告)日：2006-09-13

    申请号：EP04814618.7

    申请日：2004-12-16

    申请人： SanDisk Corporation

    发明人： LIN, Jason ,  CONLEY, Kevin, M. ,  CHANG, Robert, C.

    IPC分类号： G11C16/10

    CPC分类号： G11C16/0416 ,  G11C16/10 ,  G11C16/105 ,  G11C2216/16

    摘要： The present invention presents a non-volatile memory and method for its operation that ensures reliable mechanism for write and erase abort detection in the event of lost of power during non-volatile memory programming and erasing with minimized system performance penalty. During a multi-sector write process, an indication of a successful write in one sector is written into the overhead of the following sector at the same time as the following sector's data content is written. The last sector written will additionally have an indication of its own successful write written into its overhead. For erase, an erase abort flag in the first sector of the block can be marked after a successful erase operation.

    PIPELINED PARALLEL PROGRAMMING OPERATION IN A NON-VOLATILE MEMORY SYSTEM
    13.
    发明公开
    PIPELINED PARALLEL PROGRAMMING OPERATION IN A NON-VOLATILE MEMORY SYSTEM 有权
    EINEMNICHTFLÜCHTIGENSPEICHERSYSTEM中的管道并行计划

    公开(公告)号：EP1476812A1

    公开(公告)日：2004-11-17

    申请号：EP03713474.9

    申请日：2003-02-13

    申请人： SanDisk Corporation

    发明人： CONLEY, Kevin, M. ,  CEDAR, Yoram

    IPC分类号： G06F12/00

    CPC分类号： G11C16/105 ,  G11C16/10 ,  G11C16/102 ,  G11C2216/22

    摘要： The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller(101) to a first memory chip (131-0) and a programming operation is caused to begin. While that first memory chip (131-0) is busy performing that program operation, data is transferred from the controller(101) to a second memory chip(131-1) and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip (130-1) is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers. Two sets of embodiments are presented, one that preserves the host data in a buffer (111) until successful programming of that data is confirmed and one that does not require that success be achieved and that does not preserve the data thus achieving a higher rate of data programming throughput.

    摘要翻译： 本发明允许在非易失性存储器系统中增加编程并行性，而不会引起额外的数据传输等待时间。 数据从控制器传送到第一存储器芯片，并且开始编程操作。 当第一个存储器芯片正在忙于执行该程序操作时，数据从控制器传送到第二个存储器芯片，并且在该芯片中开始编程操作。 一旦完成编程操作，即使第二个芯片仍在忙于执行其程序操作，数据传输也可以再次开始到第一个存储器芯片。 以这种方式，实现编程操作的高并行性，而不会导致执行附加数据传输的延迟成本。 提出了两组实施例，一种将主机数据保存在缓冲器中，直到该数据的成功编程得到确认，并且不需要实现成功，并且不保留数据，从而实现更高的数据编程吞吐量 。

    POWERFULLY SIMPLE DIGITAL MEDIA PLAYER AND METHODS FOR USE THEREWITH
    15.
    发明公开
    POWERFULLY SIMPLE DIGITAL MEDIA PLAYER AND METHODS FOR USE THEREWITH 审中-公开
    强大的易于数字媒体播放器和使用，以便方法

    公开(公告)号：EP2225674A1

    公开(公告)日：2010-09-08

    申请号：EP08866064.2

    申请日：2008-12-12

    申请人： Sandisk Corporation

    发明人： CONLEY, Kevin, M. ,  SCHREIBER, Daniel ,  SHMUEL, Avraham ,  KEDEM, Noam

    IPC分类号： G06F17/30 ,  G11B27/10

    CPC分类号： G06F17/30053 ,  G06F17/30749 ,  G06F17/30772 ,  G06F17/30775 ,  G06Q30/0277 ,  G11B27/105 ,  G11B27/34

    摘要： A powerfully simple digital media player and methods for use therewith are disclosed. In one embodiment, a digital media player with a simplified user interface is disclosed that, like an FM radio, allows a user to easily select a category of digital media for playback. In another embodiment, to make the experience more FM-radio-like for a user, instead of charging the user for the digital audio files, digital media files can be distributed for free (or at a reduced charge) by playing advertisements before, during, or after the playback of a digital audio file. In yet another embodiment, an exemplary network infrastructure is provided. In another embodiment, a generic streaming content file interface is presented. Other embodiments are disclosed, and any of these embodiments can be used alone or in combination with one another.

    WRITABLE TRACKING CELLS
    17.
    发明授权
    WRITABLE TRACKING CELLS 有权
    可录制跟踪单元

    公开(公告)号：EP1332500B1

    公开(公告)日：2007-08-15

    申请号：EP01975415.9

    申请日：2001-09-25

    申请人： SanDisk Corporation

    发明人： KHALID, Shahzad, B. ,  GUTERMAN, Daniel, C. ,  GONGWER, Geoffrey, S. ,  SIMKO, Richard ,  CONLEY, Kevin, M.

    IPC分类号： G11C11/56

    CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C27/005 ,  G11C2211/5621 ,  G11C2211/5634

    摘要： The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset. In one embodiment, two populations each consisting of multiple tracking cells are associated with two logic levels of the multi-bit cell. In an analog implementation, the user cells are read directly using the analog threshold values of the tracking cell populations without their first being translated to digital values. A set of alternate embodiments provide for using different voltages and/or timing for the writing of tracking cells to provide less uncertainty in the tracking cells' final written thresholds.

    FLASH CONTROLLER CACHE ARCHITECTURE
    18.
    发明公开
    FLASH CONTROLLER CACHE ARCHITECTURE 审中-公开
    FLASH-STEUERUNGS-CACHE-ARCHITEKTUR

    公开(公告)号：EP1725937A2

    公开(公告)日：2006-11-29

    申请号：EP05724785.0

    申请日：2005-03-07

    申请人： SanDisk Corporation

    发明人： CONLEY, Kevin, M. ,  ELHAMIAS, Reuven

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0862 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/214 ,  G06F2212/2146 ,  G06F2212/282 ,  G06F2212/502

    摘要： A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, wire and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.

    摘要翻译： 介于非易失性存储器和主机之间的缓冲器高速缓存可被划分成可以用不同策略操作的段。 缓存策略包括直写，电线和预读。 直写和回写策略可能会提高速度。 Read-ahead-ahead缓存允许在缓冲区缓存和非易失性存储器之间更有效地使用总线。 会话命令允许通过保证防止功率损耗来将数据维护在易失性存储器中。

    FLASH MEMORY DATA CORRECTION AND SCRUB TECHNIQUES
    19.
    发明公开
    FLASH MEMORY DATA CORRECTION AND SCRUB TECHNIQUES 有权
    闪存存储器数据校正和擦洗技术

    公开(公告)号：EP1687720A2

    公开(公告)日：2006-08-09

    申请号：EP04785192.8

    申请日：2004-09-28

    申请人： SanDisk Corporation

    发明人： GONZALEZ, Carlos, J. ,  CONLEY, Kevin, M.

    IPC分类号： G06F11/10

    CPC分类号： G06F11/106 ,  G06F11/1068 ,  G11C8/08

    摘要： In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.

    摘要翻译： 为了保持存储在闪存中的数据的完整性，所述数据容易受到存储器的相邻区域中的操作的干扰，干扰事件导致数据在变得如此被破坏以致有效数据不能被读取，校正和重写之前被重写 被追回。 当内存系统具有其他高优先级操作执行时，通过推迟执行一些纠正措施来平衡保持数据完整性和系统性能的有时相冲突的需求。 在利用非常大的擦除单元的存储器系统中，校正过程以与高效地重写数据量比擦除单元的容量小得多的方式执行。

    PARTIAL BLOCK DATA PROGRAMMING AND READING OPERATIONS IN A NON-VOLATILE MEMORY
    20.
    发明授权
    PARTIAL BLOCK DATA PROGRAMMING AND READING OPERATIONS IN A NON-VOLATILE MEMORY 有权
    TEILDATENPROGRAMMIER-和读取操作。在非易失性存储器

    公开(公告)号：EP1352394B1

    公开(公告)日：2006-05-24

    申请号：EP02703078.2

    申请日：2002-01-07

    申请人： SanDisk Corporation

    发明人： CONLEY, Kevin, M.

    IPC分类号： G11C16/00

    CPC分类号： G11C16/102 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06F2212/7209 ,  G11C16/105 ,  G11C2216/16

    摘要： Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.