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11.发明公开
公开(公告)号：EP1794890A1
公开(公告)日：2007-06-13
申请号：EP05775794.0
申请日：2005-09-06
Inventor： JACOMET, Marcel , MÜLLER, Lorenz , CATTIN-LIEBL, Roger , GÖTTE, Josef
IPC: H03M3/02
Abstract: A digital only ΣΔ modulator comprises a node (14) which can be connected to a current source (12), representing the analog input signal, a quantizer element and a sample-and-hold element (10) mounted in series having an input (11) and an output (17), wherein said input (11) is connected to said node (14) and said output (17) representing the digital output signal, a resistor element (18) being connected between the output (17) of the sample-and-hold element (10) and said input (11) of the quantizer element (10), and a capacitance (16) connected to said node (14). Within such a sigma-delta modulator all active analog components are replaced by a single D-flip-flop. A modified 'digital-only' sigma-delta modulator, uses an additional dither generator, resulting in sigma-delta A/D converters with a significantly increased resolution. Both 'digital-only' sigma-delta modulators enable very low cost implementations in programmable logic devices and microprocessors.
Abstract translation: 一个仅数字ΣΔ调制器包括一个节点（14），它可以连接到一个表示模拟输入信号的电流源（12），一个量化器元件和一个采样保持元件（10），该元件串联安装， 其中所述输入（11）连接到所述节点（14）并且所述输出（17）表示所述数字输出信号，电阻器元件（18）连接在输出（17）和 量化器元件（10）的采样 - 保持元件（10）和所述输入（11）以及连接到所述节点（14）的电容（16）。 在这种Σ-Δ调制器内，所有有源模拟器件均由单个D触发器代替。 经过修改的'仅数字'sigma-delta调制器使用额外的抖动发生器，从而得到分辨率显着提高的sigma-delta A / D转换器。 这两种'仅数字'sigma-delta调制器在可编程逻辑器件和微处理器中实现了非常低的成本实现。
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公开(公告)号：EP1665544A1
公开(公告)日：2006-06-07
申请号：EP03758484.4
申请日：2003-09-26
Applicant: Med-El Elektromedizinische Geräte GmbH
Inventor： ZIERHOFER, Clemens, M.
IPC: H03M3/02
Abstract: A system and method for adaptive sigma-delta modulation. The system includes a input stage that produces a difference signal representing the difference between an analog input signal x(n) and a analog feedback signal z(n), the amplitude of the analog input signal x(n) within a first range [-a, +a]. An accumulator stage produces an accumulated signal that is a function of an accumulation of the difference signal, the accumulator stage transforming the accumulation of the difference signal so as to increase average magnitude while ensuring instantaneous magnitude does not exceed a predetermined value. A quantization stage produces a quantized digital signal yo(n) representing the accumulated signal. Based on the quantized digital signal yo(n), a adaptation stage produces a digital output signal zo(n), which is converted to the analog feedback signal z(n) by a digital-to-analog converter stage.
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公开(公告)号：EP0964524B1
公开(公告)日：2006-03-22
申请号：EP99111345.7
申请日：1999-06-10
Applicant: Lockheed Martin Corporation
Inventor： Pellon, Leopold Ernest
IPC: H03M3/04
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公开(公告)号：EP1504532A4
公开(公告)日：2005-07-20
申请号：EP03721907
申请日：2003-04-30
Applicant: O2MICRO INC
Inventor： LIU LIUSHENG , LI GUOXING
Abstract: An analog to digital converter (108) includes a cross switch array coupled between an input switch array and an integrator configured to alternately transfer charges from a first input capacitor and a second input capacitor to a first integration capacitor and a second integration capacitor thereby improving linearity problems caused by capacitor mismatching. The cross switch array may also be configured to transfer charges from the first input capacitor to the first integration capacitor and from the second input capacitor to the second integration capacitor during a first charge transfer time interval, and from the first input capacitor to the second integration capacitor and from the second input capacitor to the first integration capacitor during a second charge transfer time interval. A sensing system (100) including and ADC (108) consistent with the invention is also provided. Various methods of transferring charges in an ADC (108) are also provided.
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公开(公告)号：EP1304016B1
公开(公告)日：2004-09-22
申请号：EP01943541.1
申请日：2001-06-25
Applicant: Koninklijke Philips Electronics N.V.
Inventor： DIJKMANS, Eise, C.
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Patent Agency Ranking
公开(公告)号：EP0989678A3
公开(公告)日：2003-10-08
申请号：EP99118606.5
申请日：1999-09-21
Applicant: Yokogawa Electric Corporation
Abstract: An analog-to-digital converter for use with such instruments as two-wire vortex flowmeters. The converter's input terminal, adder, integrator, comparator and flip-flop circuit are connected in series, the output signal of the flip-flop circuit is connected to the converter's output terminal, and the output signal is fed back to the adder through a digital-to-analog converter. Thus the converter outputs a pulse density signal corresponding to the given input signal, serving as a sigma-delta analog-to-digital converter. The comparator's output is isolated from the input of the flip-flop circuit and the output of the flip-flop circuit is isolated from the digital-to-analog converter's input in order to reduce current consumption.
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17.发明公开Sigma-delta converter having a digital logic gate core 失效Sigma-Delta-Konverter mit einem Kern aus logischen Gattern
公开(公告)号：EP1345330A2
公开(公告)日：2003-09-17
申请号：EP03011588.5
申请日：1995-03-02
Applicant: ECHELON CORPORATION
Inventor： SUTTELRIN, Philip.H , DOWNEY, Walter.J
IPC: H03M3/02
Abstract: A sigma-delta A/D converter (301) having a digital logic gate core. The converter is comprised of a loop filter (304) for shaping the converter's quantization noise spectrum. The loop filter is comprised of an unbuffered CMOS logic gate inverter (602) which can be implemented by a gate array. A quantizer (305) is coupled to the loop filter. A logic gate buffer (501) is configured as a one-bit comparator, which is used to perform the quantization. This logic gate buffer can be one of the gates of a gate array. A sample (306) is coupled to the quantizer for sampling the quantized signal. This sampler can also be implemented by digital circuitry of a gate array. The signal from the sampler is fed into a decimator (302). The decimator outputs a digital signal representative of the amplitude of the analog signal.
Abstract translation: 具有数字逻辑门芯的Σ-ΔA/ D转换器（301）。 转换器包括用于整形转换器的量化噪声谱的环路滤波器（304）。 环路滤波器由可以由门阵列实现的无缓冲的CMOS逻辑门反相器（602）组成。 量化器（305）耦合到环路滤波器。 逻辑门缓冲器（501）被配置为用于执行量化的一比特比较器。 该逻辑门缓冲器可以是门阵列的门之一。 样本（306）耦合到量化器以对量化信号进行采样。 该采样器也可以由门阵列的数字电路实现。 来自采样器的信号被馈送到抽取器（302）中。 抽取器输出代表模拟信号幅度的数字信号。
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公开(公告)号：EP1300951A2
公开(公告)日：2003-04-09
申请号：EP02021937.4
申请日：2002-09-29
Applicant: Gude, Michael, Dr.
Inventor： Gude, Michael, Dr.
IPC: H03M3/02
Abstract: Die vorliegende Erfindung liegt die Aufgabe zu Grunde, den analogen Teil eines einfachen Delta-Sigma A/D-Wandlers (analoges Frontend) soweit zu verbessern, dass bei Beibehaltung des einfachen Aufbaus eine erhebliche Steigerung der Auflösung möglich wird.
Diese Aufgabe wird erfindungsgemäß dadurch gelöst, dass ein vor dem D-Eingang des Flip-Flops [4] im Rückkopplungspfad befindlicher Buffer [5][7] und/oder ein hinter dem Ausgang des Flip-Flops [4] befindlicher Buffer [6][8] betriebsspannungsmäßig getrennt von dem die digitalen Schaltungsteile beinhaltenden Halbleiterchip versorgt wird, damit eine Entkopplung zwischen Halbleiterchip und analogem Frontend eintritt. In einer weiteren Ausprägung der Erfindung wird dafür gesorgt, dass die außerhalb des Halbleiterchips auftretenden Frequenzen viel kleiner als die Abtastfrequenz des Flip-Flops [4] werden. Dadurch ist es möglich die interne Abtastfrequenz bis in den GigaHz-Bereich zu steigern ohne Probleme mit der elektromagnetischen Verträglichkeit zu bekommen.Abstract translation: 本发明所基于的物体上时，一个简单的Δ-Σ的模拟部分的A / D转换器，以改善（模拟前端）的范围内，同时保持简单的结构分辨率的显著增加是可能的。 该目的创造性地在一到触发器的D输入达到befindlicher现有[4]在反馈路径中缓冲液[5] [7]和/或触发器的输出后面的befindlicher [4]缓冲液[6] [8]是提供的操作电压从含有半导体芯片的数字电路部分过度分离，从而使半导体芯片和模拟前端之间的去耦发生。 在本发明的另一实施例，确保了半导体芯片以外发生的频率比触发器[4]的采样频率小得多。 这使得内部采样频率高达GigaHz区中而不与电磁兼容性得到越来越多的问题。
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公开(公告)号：EP0993123A3
公开(公告)日：2002-01-30
申请号：EP99307670.2
申请日：1999-09-29
Applicant: KABUSHIKI KAISHA TOSHIBA
CPC classification number: H03M1/0668 , H03M1/747 , H03M3/40 , H03M3/41 , H03M3/424 , H03M3/456 , H03M3/464
Abstract: A subtraction section (103) subtracts a first signal from a second signal as a harmonic signal and outputs a third signal as a subtraction result. A first conversion section (105, 106, 107, 108) converts the third signal into a digital signal of predetermined frequency different from a frequency of the second signal. A second conversion section (109, 110, 111, 113) converts the digital signal into an analog signal of a frequency nearly equal to the frequency of the second signal and supplies the analog signal as the first signal to the subtraction section (103). The second conversion section (109, 110, 111, 113) includes a plurality of conversion elements, a filter to calculate a number of use of each of the plurality of conversion elements, and a selector (113) to select the conversion elements having a lower value of the number of use. The number of conversion elements selected corresponds to the value of the digital signal.
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20.发明授权METHOD AND APPARATUS FOR MULTIPLEXED OVERSAMPLED ANALOG TO DIGITAL MODULATION 失效对于多路复用的方法和装置的过采样模拟和数字调制
公开(公告)号：EP0641502B1
公开(公告)日：2000-07-05
申请号：EP93913911.9
申请日：1993-05-17
Applicant: MANDL, William J.
Inventor： MANDL, William J.
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