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    High speed magnetic random access memory-based ternary CAM
    14.
    发明公开
    High speed magnetic random access memory-based ternary CAM 有权
    高速磁性随机存取存储器的基于三元CAM

    公开(公告)号：EP2626861A1

    公开(公告)日：2013-08-14

    申请号：EP12290052.5

    申请日：2012-02-13

    申请人： Crocus Technology S.A.

    发明人： Alvarez-Hérault, Jérémy ,  Conraux, Yann ,  Lombard, Lucien

    IPC分类号： G11C11/16 ,  G11C11/56 ,  G11C15/02

    CPC分类号： G11C15/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C15/046 ,  G11C2211/5615

    摘要： The present disclosure concerns a self-referenced magnetic random access memory-based ternary content addressable memory (MRAM-based TCAM) cell (1) comprising a first and second magnetic tunnel junction (2, 2'); a first and second conducting strap (7, 7') adapted to pass a heating current (31) in the first and second magnetic tunnel junction (2, 2'), respectively; a conductive line (3) electrically connecting the first and second magnetic tunnel junctions (2, 2') in series; a first current line (4) for passing a first field current (41) to selectively write a first write data to the first magnetic tunnel junction (2); and a second current line (4') for passing a write current (31, 41') to selectively write a second write data to the second magnetic tunnel junction (2'), such that three distinct cell logic states can be written in the MRAM-based TCAM cell (1).

    System for updating an associative memory
    15.
    发明公开
    System for updating an associative memory 有权
    系统zur Aktualisierung eines assoziativen Speichers

    公开(公告)号：EP2551854A1

    公开(公告)日：2013-01-30

    申请号：EP12177203.2

    申请日：2012-07-20

    申请人： The Boeing Company

    发明人： Nakamoto, Kyle Masao ,  Quadracci, Leonard Jon

    IPC分类号： G11C15/00

    CPC分类号： G11C15/00 ,  G06F17/30982

    摘要： A system (100) includes an associative memory (102), a first table (134), a second table (136), a comparator (164), and an updater (166). The associative memory (102) may include data and associations among data and may be built from the first table (134). The first table (134) may include a record (144) with a first and second field (150, 152). The associative memory may be configured to ingest the first field (150) and avoid ingesting the second field (152). The second table (136) may include a record (160) with a third field (162) storing information indicating whether the first field (150) has been ingested by the associative memory (102) or has been forgotten by the associative memory (102). The comparator (164) may be configured to compare the first and second table (134, 136) to identify one of whether the first field (150) should be forgotten or ingested by the associative memory (102). The updater (166) may be configured to update the associative memory (102) by performing one of ingesting or forgetting the first field (150).

    摘要翻译： 系统（100）包括关联存储器（102），第一表（134），第二表（136），比较器（164）和更新器（166）。 关联存储器（102）可以包括数据之间的数据和关联，并且可以从第一表（134）构建。 第一表（134）可以包括具有第一和第二场（150,152）的记录（144）。 关联存储器可以被配置为摄取第一场（150）并避免摄取第二场（152）。 第二表（136）可以包括具有第三字段（162）的记录（160），该第三字段（162）存储指示第一字段（150）是否已经被关联存储器（102）摄取或被关联存储器（102 ）。 比较器（164）可以被配置为比较第一和第二表（134,136）以识别第一场（150）是否应被关联存储器（102）遗忘或摄取之一。 更新器（166）可以被配置为通过执行摄取或遗忘第一场（150）来更新关联存储器（102）。

    HIERARCHICAL IMMUTABLE CONTENT-ADDRESSABLE MEMORY PROCESSOR
    16.
    发明公开
    HIERARCHICAL IMMUTABLE CONTENT-ADDRESSABLE MEMORY PROCESSOR 审中-公开
    联合国难民事务高级专员

    公开(公告)号：EP2115593A4

    公开(公告)日：2013-01-09

    申请号：EP08724801

    申请日：2008-01-24

    申请人： HICAMP SYSTEMS INC

    发明人： CHERITON DAVID R

    IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/10 ,  G11C15/00 ,  G11C15/04

    CPC分类号： G06F3/064 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673 ,  G06F12/0223 ,  G06F12/023 ,  G06F12/0261 ,  G06F12/0815 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/1044 ,  G06F2212/621 ,  G11C15/00 ,  G11C15/04

    摘要： Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

    摘要翻译： 根据分层不可变内容可寻址内存处理器（HICAMP）架构提供了改进的内存管理。 在HICAMP中，物理存储器被组织为两个或多个物理存储器块，每个物理存储器块具有固定的存储容量。 提供了在任何时间点哪个物理存储器块处于活动状态的指示。 存储器控制器提供非复制写入能力，其中要写入物理存储器的数据与写入时的所有活动物理存储器块的内容进行比较，以确保在完成后没有两个活动存储器块具有相同的数据 的非重复写入。

    Power limiting in a content search system
    17.
    发明公开
    Power limiting in a content search system 审中-公开
    Leistungsbegrenzung在einem Inhaltssuchsystem

    公开(公告)号：EP2503555A1

    公开(公告)日：2012-09-26

    申请号：EP12001681.1

    申请日：2012-03-12

    申请人： Netlogic Microsystems, Inc.

    发明人： Channabasappa, Shankar

    IPC分类号： G11C5/14 ,  G11C15/00 ,  G06F1/32

    CPC分类号： G11C15/04 ,  G06F1/3275 ,  G11C5/14 ,  G11C15/00 ,  Y02D10/13 ,  Y02D10/14

    摘要： A content search system including a CAM device having a plurality of CAM blocks and a governor logic receives a search request and compares the number of CAM blocks required to perform the requested search to a limit number, the limit number being the maximum number of CAM blocks permitted to be used in a requested search operation. If the number of CAM blocks required to perform the requested search exceeds the maximum number of CAM blocks permitted to be used in a requested search operation, then the search operation is rejected. The governing operation can be performed on each requested search, thus limiting power dissipation. The relationship between a maximum number of CAM blocks and power dissipation can be characterized, and a corresponding block limit value can be stored into a memory accessible by governor logic.

    摘要翻译： 包括具有多个CAM块和调速器逻辑的CAM装置的内容搜索系统接收搜索请求，并将执行所请求的搜索所需的CAM块的数量与限制数进行比较，该限制数是CAM块的最大数量 允许在请求的搜索操作中使用。 如果执行所请求的搜索所需的CAM块的数量超过在所请求的搜索操作中允许使用的最大CAM数量，那么搜索操作被拒绝。 可以对每个请求的搜索执行调节操作，从而限制功耗。 可以表征最大数量的CAM块和功耗之间的关系，并且可以将相应的块限制值存储到由调速器逻辑可访问的存储器中。

    CONTENT ASSEMBLY MEMORY AND METHOD
    19.
    发明公开
    CONTENT ASSEMBLY MEMORY AND METHOD 有权
    目录编制存储器和方法

    公开(公告)号：EP2382635A1

    公开(公告)日：2011-11-02

    申请号：EP09799719.1

    申请日：2009-12-22

    申请人： Telefonaktiebolaget L M Ericsson (PUBL)

    发明人： HORNER, Jeremy

    IPC分类号： G11C15/04 ,  G06F12/10 ,  G06F17/30 ,  H04L12/56

    CPC分类号： H04L45/00 ,  G11C15/00 ,  H04L45/7453

    摘要： A content addressable memory (CAM) includes ports through which keys having at least a 16 bit function are received or transmitted. The CAM includes a processing unit in communication with the ports. The CAM includes a storage portion in which the keys are stored in communication with a processing unit. The CAM includes a programmable key update mechanism in communication with the processing unit which updates the keys without the keys leaving the CAM. A method for using a content addressable memory (CAM) includes the steps of receiving keys having at least a 16 bit function at a port. There is the step of storing the keys in a storage portion in communication with a processing unit. There is the step of updating the keys without the keys leaving the CAM with a programmable key update mechanism in communication with a processing unit.

    A content addressable memory cell
    20.
    发明公开
    A content addressable memory cell 有权
    关于可选内容存储单元

    公开(公告)号：EP2261928A3

    公开(公告)日：2011-04-20

    申请号：EP10183801.9

    申请日：2003-10-22

    申请人： STMicroelectronics S.r.l. ,  Ovonyx Inc.

    发明人： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC分类号： G11C15/04 ,  G11C14/00

    CPC分类号： G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    摘要： A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.