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公开(公告)号：EP1168362A3
公开(公告)日：2004-09-29
申请号：EP01121238.8
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A flash memory comprises a cell matrix, in which rewritable nonvolatile memory cells (591ij) are arranged at intersections between a plurality of word lines (WLi) and a plurality of bit lines (BLi), and also comprises row decoders (587) for applying specified voltage selectively to the word lines (WLi) during writing or reading. The flash memory further comprises: switch circuits (590i) that are located between the cell matrix and the row decoder (587) in association with the word lines, and that enter a cutoff state when the word lines are set to negative voltage and enter a conducting state on any other occasion; negative-voltage bias circuits (592) whose negative-voltage output terminals (554) are connected to the word lines (WLi), and that apply the voltage output of a negative power supply to the word lines in response to a clock pulse (CLK) ; and clock pulse control circuits (593, 594) for causing the clock pulse (CLK) to be supplied to the negative-voltage bias circuit when it is detected during erasing that the word lines (WLi) are selected. The word lines (WLi) are divided into a plurality of groups and the clock pulse control circuits (593, 594) are operable to cause the clock pulse (CLK) to be supplied to each of the negative-voltage bias circuits connected to the selected word lines in a group when any word lines in the group are selected.
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公开(公告)号：EP1041720B1
公开(公告)日：2004-09-15
申请号：EP00302108.6
申请日：2000-03-15
申请人： FUJITSU LIMITED
CPC分类号： G06F9/30032 , G06F7/02
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公开(公告)号：EP0949761B1
公开(公告)日：2004-03-03
申请号：EP99400834.0
申请日：1999-04-06
IPC分类号： H03K19/096 , H03K19/21
CPC分类号： H03K19/215 , H03K19/0963
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公开(公告)号：EP0961289B1
公开(公告)日：2002-10-02
申请号：EP99115179.6
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A negative-voltage bias circuit is provided which comprises: a capacitor (550) having first and second terminals (550B, 550A) ; a first p-channel MIS field-effect transistor (551) whose drain is connected to a negative-voltage output terminal (554) and whose gate and source are connected to the first terminal (550B) of the capacitor (550); and a second p-channel MIS field-effect transistor (552) whose drain is connected to the source of the first p-channel MIS field effect transistor (551), whose gate is connected to the negative-voltage output terminal (554), and whose source is provided with a negative voltage (VBB). The first p-channel MIS field-effect transistor (551) is a depletion-type p-channel MIS field-effect transistor. In operation of the circuit, application to the second terminal (550A) of a series of clock pulses (CLK) causes a potential of the negative-voltage output terminal (554) to tend towards the negative voltage (VBB).
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公开(公告)号：EP1141841A4
公开(公告)日：2002-02-06
申请号：EP99937438
申请日：1999-07-23
发明人： MROS STANLEY P , JENKINS KEVIN J
IPC分类号： G06F3/00 , G06F13/40 , H03K19/0175 , G06F13/00 , G06F13/14 , H02J1/16 , H03K17/16 , H03K19/003 , H03K19/082 , H03K19/21
CPC分类号： G06F13/4081
摘要： A hot-swappable point-to-point connection between high speed transmitter (28) on transmitter card (22) and high speed receiver (32) on receiver card (24) is provided. Transmitter card (22) and receiver card (24) can be inserted into backplane (26) forming connection (36) between transmitter (28) and receiver (32). Power indicator (64) on transmitter card (22) indicates if power is applied to transmitter card (22). Receiver switch (60) on receiver card (24) has control input (62) connected to power indicator (64) when both receiver card (24) and transmitter card (22) are inserted in backplane (26). Receiver switch (60) enables receiver (32) when control input (62) is asserted. Likewise, second power indicator (54) on receiver card (24) connects to control input (52) of transmitter switch (50) on transmitter card (22).
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公开(公告)号：EP1141841A1
公开(公告)日：2001-10-10
申请号：EP99937438.2
申请日：1999-07-23
IPC分类号： G06F13/00 , G06F13/14 , H02J1/16 , H03K17/16 , H03K19/003 , H03K19/0175 , H03K19/082 , H03K19/21
CPC分类号： G06F13/4081
摘要： A hot-swappable point-to-point connection between high speed transmitter (28) on transmitter card (22) and high speed receiver (32) on receiver card (24) is provided. Transmitter card (22) and receiver card (24) can be inserted into backplane (26) forming connection (36) between transmitter (28) and receiver (32). Power indicator (64) on transmitter card (22) indicates if power is applied to transmitter card (22). Receiver switch (60) on receiver card (24) has control input (62) connected to power indicator (64) when both receiver card (24) and transmitter card (22) are inserted in backplane (26). Receiver switch (60) enables receiver (32) when control input (62) is asserted. Likewise, second power indicator (54) on receiver card (24) connects to control input (52) of transmitter switch (50) on transmitter card (22).
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17.发明公开Logic circuit and full adder using the same 审中-公开Logikschaltkreis und Volladdierer mit einem derartigen Schaltkreis
公开(公告)号：EP1111791A1
公开(公告)日：2001-06-27
申请号：EP00403396.5
申请日：2000-12-04
申请人： SONY CORPORATION
发明人： Kouji, Hirairi
CPC分类号： G06F7/501 , H03K19/215
摘要： A logic circuit capable of suppressing occurrence of wraparound of signals. capable of reducing power consumption, and in addition achieving a reduction of a circuit scale and an improvement of an operating speed and a full adder using the same, wherein provision is made of an exclusive-OR generation circuit (12) for receiving a first logic signal A and a second logic signal B taking a logic "1" or "0" and generating the exclusive-OR of the first logic signal A and the second logic signal B, a dual signal generation circuit (11) for receiving the first logic signal A and the second logic signal B and generating the dual signal of the exclusive-OR of the first logic signal A and the second logic signal B. and an interpolation circuit (13) for compulsorily setting the output level of the dual signal at the level of the logic "1" when the output level of the exclusive-OR is the logic "0", while compulsorily setting the output level of the exclusive-OR at the level of the logic "0" when the output level of the dual signal is the logic "1",
摘要翻译： 一种能够抑制信号环绕的发生的逻辑电路。 能够降低功耗，另外实现电路规模的缩小和工作速度的提高以及使用其的全加器，其中提供了异或产生电路（12），用于接收第一逻辑 信号A和逻辑“1”或“0”并产生第一逻辑信号A和第二逻辑信号B的异或的第二逻辑信号B，用于接收第一逻辑信号的双信号产生电路 信号A和第二逻辑信号B，并产生第一逻辑信号A和第二逻辑信号B的异或的双信号;以及插值电路（13），用于强制地将双信号的输出电平设置在 当异或的输出电平为逻辑“0”时逻辑“1”的电平，同时在双向输出的输出电平时强制将异或的输出电平设置在逻辑“0”的电平 信号是逻辑“1”，
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公开(公告)号：EP0949761A1
公开(公告)日：1999-10-13
申请号：EP99400834.0
申请日：1999-04-06
IPC分类号： H03K19/096 , H03K19/21
CPC分类号： H03K19/215 , H03K19/0963
摘要： La présente invention concerne le domaine des équipements de traitement de données comprenant éventuellement, dans certaines applications un ensemble d'unités de traitement à commandes communes et a notamment pour objet un dispositif de traitement de deux informations binaires A et B en vue de l'obtention d'une conjonction ou d'une disjonction de ces valeurs et/ou de leur complémentaire, les deux informations binaires A et B étant stockées respectivement dans des points mémoire semi-statique Ga et Gb appartenant ou non à un même registre à décalage, chacun de ces points mémoire comportant deux inverseurs I1 et I2 installés dans le même sens de rotation, la sortie de I1 étant connectée à l'entrée de I2 à travers un interrupteur TM1 et la sortie de I2 étant connectée à l'entrée de I1 à travers un interrupteur TM2, la tension en sortie de I2 étant représentative de l'information binaire du point, caractérisé en ce qu'il comporte des moyens (Tc) de commutation commandés aptes à connectés l'entrée de l'un des inverseurs (I1, I2) du point mémoire Ga à l'entrée de l'un des inverseurs (I1, I2) du point mémoire Gb, et des moyens de seuillage connectés à l'une au moins des dites entrées des inverseurs.
摘要翻译： 从每个存储器存储中的输出电容被混合以产生代表两个输出的电压的电平。
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公开(公告)号：EP0939490A2
公开(公告)日：1999-09-01
申请号：EP99102710.3
申请日：1999-02-18
发明人： Sakata, Kouji
IPC分类号： H03K19/21
CPC分类号： H03K19/215 , G06F7/02
摘要： A comparator compares a first data word with a second data word. The comparator includes first stage of two input XOR gates (21A0-21A1), each of which receive one bit of the first word and a corresponding bit of the second word, and output a coincidence detection signal. A first inverter circuit (23) receives a control signal and generates an inverted control signal. A decision circuit (24) receives the inverted control signal and each of the coincidence detection signals, and generates a decision circuit output signal. A two input NAND gate (28) receives the decision circuit output signal and the control signal and generates a comparator output signal. The decision circuit includes an inverter circuit (25) that receives the inverted control signal from the first inverter circuit and a series of transistors (TN0-TNn-1) connected between the inverter circuit output terminal and ground. The gates of the transistor receive the respective coincidence detection signals.
摘要翻译： 比较器将第一数据字与第二数据字进行比较。 比较器包括两个输入XOR门（21A0-21A1）的第一级，其中每一个接收第一字的一位和第二字的对应位，并输出一致检测信号。 第一逆变器电路（23）接收控制信号并产生反相控制信号。 判定电路（24）接收反相控制信号和每个重合检测信号，并产生判定电路输出信号。 两输入NAND门（28）接收判定电路输出信号和控制信号，并生成比较器输出信号。 决定电路包括从第一反相器电路接收反相控制信号的反相器电路和连接在反相器电路输出端子与地之间的一系列晶体管（TN0-TNn-1）。 晶体管的栅极接收相应的重合检测信号。
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20.发明公开
公开(公告)号：EP0905907A1
公开(公告)日：1999-03-31
申请号：EP98402263.2
申请日：1998-09-14
发明人： Marbot, Roland , Couteaux, Pascal
CPC分类号： H03K19/215 , H03K5/00006
摘要： La présente invention concerne une porte logique OU-Exclusif à quatre entrées complémentaires deux à deux (A, NA et B, NB) et à deux sorties complémentaires (XOR et NXOR), dont la structure est dite symétrique en ce que la porte présente un temps de propagation identique quelle que soit celui des couples d'entrées qui commute, quelle que soit la nature de la transition, et quel que soit l'état logique du couple d'entrées qui ne commute pas. L'invention permet de réduire encore les écarts du temps de propagation des fronts à travers la porte en supprimant le caractère flottant de certains noeuds. Elle concerne aussi un multiplieur de fréquence comportant un arbre de telles portes OU-Exclusif.
摘要翻译： 平行于每个分支（P10，P20; N10，N20）有一个第二双分支（P11，P21; N11，N21），其中所述第一和第二晶体管接收的命令网格反相输入和连接到所述第一分支组 ，因此，在这将被视为从初值此前节点去除可变电荷水平。
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