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34 条记录 (耗时 0.015 秒)

    Structure and process for fabrication of stacked complementary MOS field effect transistor devices
    24.
    发明公开
    Structure and process for fabrication of stacked complementary MOS field effect transistor devices 失效
    堆叠补充MOS场效应晶体管器件的结构和工艺

    公开(公告)号：EP0066068A3

    公开(公告)日：1985-09-18

    申请号：EP82103172

    申请日：1982-04-15

    申请人： International Business Machines Corporation

    发明人： Bansal, Jai Pal ,  Bertin, Claude Louis ,  Troutman, Ronald Roy

    IPC分类号： H01L27/06 ,  H01L21/82

    CPC分类号： H01L21/8238 ,  H01L21/268 ,  H01L27/0688 ,  H01L27/0922 ,  H01L29/04

    摘要： A method for fabricating a stacked complementary MOSFET device comprising the steps of:
    depositing a layer of phosphosilicate glass (58) on top of the gate electrode (56) of an N channel FET device (4) formed in the surface of a monocrystalline silicon substrate (50) having source (60) and drain (62) diffusions in said substrate on either side of said gate; depositing a layer of P-type polycrystalline silicon (65) over said phosphosilicate glass layer (58), extending over said source (60) and drain (62) diffusions and physically contacting a portion of the surface of said monocrystalline silicon substrate (50); heating said polycrystalline silicon layer (65) including said portion contacting said substrate (50) to a recrystallization temperature; cooling and recrystallizing said polycrystalline silicon layer (65) into a monocrystalline silicon form having a lattice orientation epitaxially reoriented to the lattice orientation of said monocrystalline semiconductor substrate (50); heating said phosphosilicate glass layer (58) so as to diffuse phosphorous atoms from said phosphosilicate glass layer upwardly into said silicon layer (65), forming an N-type region (78) which is juxtaposed with said gate electrode (56) and is self-aligned to said gate electrode. The structure of the complementary MOSFET device comprises an upper, P channel FET device (6) which is formed in said silicon layer (65), and which shares said gate electrode (56) with said N channel FET device (4).

    Machine structures fabricated of multiple microstructure layers
    26.
    发明公开
    Machine structures fabricated of multiple microstructure layers 失效
    机结构由多个微结构层的

    公开(公告)号：EP0757431A3

    公开(公告)日：1997-10-08

    申请号：EP96305180.0

    申请日：1996-07-15

    申请人： International Business Machines Corporation

    发明人： Bertin, Claude Louis ,  Cronin, John Edward

    IPC分类号： H02N1/00

    CPC分类号： H01H1/0036 ,  H02N1/004

    摘要： Machine structures each comprising a stack of a plurality of micromachine layers laminated together are presented, along with fabrication methods therefore. Each machine structure includes a movable member(s) defined from microstructure of at least one layer of the plurality of micromachine layers comprising the stack. During fabrication, the micromachine layers are separately formed using VLSI techniques and then subsequently laminated together in a selected arrangement in the stack to define the machine structure.

    Method and apparatus for a stress relieved electronic module
    28.
    发明公开
    Method and apparatus for a stress relieved electronic module 失效
    Verfahren und Apparatfüreinen elektronischen Modul ohne Spannungen

    公开(公告)号：EP0706219A1

    公开(公告)日：1996-04-10

    申请号：EP95480112.2

    申请日：1995-08-08

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Bertin, Claude Louis ,  Farrar, Paul Alden ,  Kelley, Gordon Arthur, Jr. ,  Miller, Christopher Paul

    IPC分类号： H01L25/065 ,  H01L21/98 ,  H01L29/06

    CPC分类号： H01L29/0657 ,  H01L24/01 ,  H01L25/0657 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

    摘要： A fabrication method and resultant electronic module (21) that facilitates relief of thermally induced stress within the module. The fabrication method includes providing a plurality of integrated circuit chips (11) having grooves in substantially planar main surfaces (13) thereof. The chips are stacked and bonded to each other using an expandable material and a flowable adhesive to form an electronic module. The bonding is such that movement of individual IC chips within the module, in a direction perpendicular to their planar surfaces, is restricted. Upon thermal expansion of the module, the expandable material and the individual chips expand at different rates. However, the expandable material flows into the grooves, relieving thermally induced stress.

    摘要翻译： 一种制造方法和产生的电子模块（21），其有助于减轻模块内的热诱导应力。 该制造方法包括在其基本平坦的主表面（13）中提供具有凹槽的多个集成电路芯片（11）。 使用可膨胀材料和可流动的粘合剂将芯片堆叠并彼此粘合以形成电子模块。 结合使得单独的IC芯片在模块内沿垂直于它们的平面的方向的移动受到限制。 在模块的热膨胀时，可膨胀材料和各个芯片以不同的速率膨胀。 然而，可膨胀材料流入沟槽，减轻热致应力。

    Polyimide-insulated cube package of stacked semiconductor device chips
    29.
    发明公开
    Polyimide-insulated cube package of stacked semiconductor device chips 失效
    Kubikpackung mit Polyimidisolierung von gestapelten Halbleiterchips。

    公开(公告)号：EP0631310A1

    公开(公告)日：1994-12-28

    申请号：EP94108520.1

    申请日：1994-06-03

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Bertin, Claude Louis ,  Farrar,Sr.,Paul Alden ,  Howell, Wayne John ,  Miller, Christopher Paul ,  Perlman, David Jacob

    IPC分类号： H01L21/98 ,  H01L25/065

    CPC分类号： H01L25/50 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    摘要： A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face (16) to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer (9) is insulated from the chip face and from the adjacent chip in the stack by polymer layers (16) having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

    摘要翻译： 堆叠硅半导体芯片的立方体封装。 为了容纳立方体包装，在钝化的芯片面（16）上添加金属转移层，以使所有的表面电触点成为共同的芯片边缘。 金属转移层（9）通过具有低介电常数的聚合物层（16）和与堆叠芯片的热膨胀系数相匹配的聚合物层（16）与芯片表面和堆叠中的相邻芯片绝缘。 添加粘合剂聚合物层以通过沉积粘合剂层并在晶片级上部分固化来增强第一聚合物层和叠层中的相邻芯片之间的结合，然后当芯片堆叠在一起形成时，完全固化 立方体。

    Three-dimensional direct-write EEPROM arrays and fabrication methods
    30.
    发明公开
    Three-dimensional direct-write EEPROM arrays and fabrication methods 失效
    Dreidimensionale EEPROM-Matrizen zum direkten Schreiben und Herstellungsverfahren。

    公开(公告)号：EP0562257A1

    公开(公告)日：1993-09-29

    申请号：EP93102131.5

    申请日：1993-02-11

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Bertin, Claude Louis ,  DiMaria, Donelli Joseph ,  Miyakawa, Makoto ,  Sakaue, Yoshinori

    IPC分类号： H01L27/115 ,  H01L29/788

    CPC分类号： H01L29/7882 ,  H01L27/115 ,  H01L27/11556

    摘要： A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches (30) formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate (RG) and a program gate (PG) with another cell in the same trench. Preferably, a silicon rich dielectric (43) (such as silicon rich oxide or silicon rich nitride) disposed between each floating gate (FG) and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

    摘要翻译： 公开了一种适用于具有直写单元能力的电可擦除可编程只读存储器（EEPROMS）的三维存储单元。 存储单元用于制造具有高集成密度的非易失性，直写式EEPROM阵列。 典型的EEPROM阵列包括形成在半导体衬底中的多个细长的浅沟槽（30）。 多个直写EEPROM单元被布置在每个细长沟槽内，使得每个EEPROM单元与相同沟槽中的另一个单元共享回调门（RG）和编程门（PG）。 优选地，设置在每个浮置栅极（FG）与其相关联的编程和调用栅极之间的富硅电介质（43）（诸如富硅氧化物或富含硅的氮化物）。 公开了源极扩散和隔离源扩散实施例。 此外，描述了所呈现的用于直写EEPROM阵列的各种制造方法。