公开(公告)号：EP3278456A1

公开(公告)日：2018-02-07

申请号：EP15787783.8

申请日：2015-10-12

申请人： Xilinx, Inc.

发明人： KARP, James ,  KIREEV, Vassili

IPC分类号： H03K19/173 ,  H01L25/00

CPC分类号： H01L23/5382 ,  H01L23/3121 ,  H01L23/5386 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/18 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/1431 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19107 ,  H03K19/1732 ,  H01L2924/014 ,  H01L2924/00014

摘要： Various example implementations are directed to circuits and methods for inter-die communication on a multi-die integrated circuit (IC) package. According to an example implementation, an IC package includes a first semiconductor die having a plurality of communication circuits for communicating data over respective data terminals of the package. The package also includes a second semiconductor die having N contacts for communicating data to and from the semiconductor die. The second semiconductor die includes a logic circuit configured to communicate M parallel data signals with one or more other semiconductor dies of the package, wherein M>N. The second semiconductor die also includes a plurality of serializer circuits, each configured to serialize data from a respective subset of the plurality of the M signal lines to produce serialized data and provide the serialized data to a respective one of the contacts.

公开(公告)号：EP2811514A2

公开(公告)日：2014-12-10

申请号：EP14001300.4

申请日：2014-04-09

申请人： Fairchild Semiconductor Corporation

发明人： Ashrafzadeh, Ahmad ,  Ullal, Vijay ,  Chiang, Justin ,  Kinzer, Daniel ,  Dube, Michael M. ,  Jeon, Oseob ,  WU, Chung-Lin ,  Estacio, Maria Cristina

IPC分类号： H01L23/31

CPC分类号： H01L25/0652 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/19 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2225/06531 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2924/00

摘要： In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.

摘要翻译： 在一个一般方面，一种方法可以包括使用第一电镀工艺在衬底上形成再分布层，以及使用第二电镀工艺在再分配层上形成导电柱。 该方法可以包括将半导体管芯耦合到再分配层，并且可以包括形成封装再分布层的至少一部分和导电柱的至少一部分的模制层。

公开(公告)号：EP1481424B1

公开(公告)日：2013-09-25

申请号：EP03742896.8

申请日：2003-02-21

申请人： Legacy Electronics, Inc.

发明人： KLEDZIK, Kenneth ,  ENGLE, Jason, C.

IPC分类号： H01L25/065 ,  H01L25/10

CPC分类号： H05K1/141 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/144 ,  H05K1/182 ,  H05K1/183 ,  H05K3/3436 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/09954 ,  H05K2201/10515 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01005

公开(公告)号：EP1921904B1

公开(公告)日：2013-06-12

申请号：EP06766615.6

申请日：2006-06-13

申请人： MURATA MANUFACTURING CO., LTD.

发明人： MATSUBARA, Daigo ,  CHIKAGAWA, Osamu

IPC分类号： H05K3/46 ,  H01L23/13

CPC分类号： H05K3/4007 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2201/0979 ,  H05K2203/308 ,  Y10T29/49163 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A ceramic electronic component is provided which can realize a sufficient drop resistance strength even when terminal electrodes are formed at a higher density. A ceramic electronic component 10 of the present invention has a ceramic laminate 11 composed of ceramic laminates 11A which are laminated to each other, first terminal electrodes 13 disposed in a peripheral portion of a bottom surface of the ceramic laminate 11, catch pad electrodes 15A provided in the ceramic laminate 11 to face the respective first terminal electrodes 13, and sets each including at least two first via hole conductors 16A and 16B, which electrically connect the first terminal electrodes 13 and the respective catch pad electrodes 15A.

公开(公告)号：EP2546873A2

公开(公告)日：2013-01-16

申请号：EP12171592.4

申请日：2012-06-12

申请人： Elpida Memory, Inc.

发明人： Sato, Homare

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/1532

摘要： Disclosed herein is a semiconductor device that includes: a first circuit formed on a chip having a main surface; first to n th penetration electrodes penetrating through the chip, where n is an integer more than 1; first to n th main terminals arranged on the main surface of the chip and vertically aligned with the first to n th penetration electrodes, respectively, each of k th main terminal being electrically connected to k+1 th penetration electrode, where k is an integer more than 0 and smaller than n, and the n th main terminal being electrically connected to the first penetration electrode; a sub-terminal arranged on the main surface of the chip; and a selection circuit electrically connected to predetermined one of the first to n th main terminals, the sub-terminal, and the first circuit, wherein the selection circuit connects the first circuit to one of the predetermined main terminal and the sub-terminal.

摘要翻译： 本文公开了一种半导体器件，其包括：形成在具有主表面的芯片上的第一电路; 第一至第n穿透芯片的穿透电极，其中n是大于1的整数; 第一至第n主端子，设置在芯片的主表面上并分别与第一至第n穿透电极垂直对齐，每个第k主端子电连接至第k + 1个穿透电极，其中k是大于0的整数;以及 小于n，并且第n主端子电连接到第一穿透电极; 布置在芯片的主表面上的子端子; 以及电连接到第一至第n主端子，子端子和第一电路中预定的一个的选择电路，其中选择电路将第一电路连接到预定主端子和子端子中的一个。

公开(公告)号：EP2105961A3

公开(公告)日：2012-10-31

申请号：EP09004461.1

申请日：2009-03-27

申请人： Broadcom Corporation

发明人： Rofougaran, Ahmadreza

IPC分类号： H01L23/66 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/49816 ,  H01L23/5383 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L2223/6627 ,  H01L2223/6688 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/014

摘要： Methods and systems for inter-chip communication via integrated circuit package waveguides are disclosed and may include communicating one or more signals between or among a plurality of integrated circuits via one or more waveguides integrated in a multi-layer package. The integrated circuits may be bonded to the multi-layer package. The waveguides may be configured via switches in the integrated circuits or by MEMS switches integrated in the multi-layer package. The signals may include a microwave signal and a low frequency control signal that may configure the microwave signal. The low frequency control signal may include a digital signal. The waveguides may comprise metal and/or semiconductor layers deposited on and/or embedded within the multi-layer package.

公开(公告)号：EP2450950A2

公开(公告)日：2012-05-09

申请号：EP12153057.0

申请日：2003-03-27

申请人： Intel Corporation

发明人： Vandentop, Gilroy ,  Chiu, Chia-Pin ,  Nair, Rajendran ,  Li, Yian-Liang

IPC分类号： H01L23/367 ,  H01L23/40 ,  H01L23/538 ,  H05K1/02 ,  H01L23/498

CPC分类号： H01L23/4006 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4093 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2023/405 ,  H01L2023/4056 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/732 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19042 ,  H05K1/0204 ,  H05K1/182 ,  H05K2201/09054 ,  H05K2201/10378 ,  H05K2201/10409 ,  H05K2201/10477 ,  H05K2201/10734 ,  H05K2203/1572

摘要： The present invention describes a method and apparatus for mounting a microelectronic device parallel to a substrate with an interposer and two heat sinks, one on each side of the substrate.

摘要翻译： 本发明描述了一种用于将微电子器件平行于具有插入器和两个散热器的衬底安装的方法和装置，每个衬底的每一侧上都有一个。

公开(公告)号：EP2226841A9

公开(公告)日：2011-11-16

申请号：EP08868979.9

申请日：2008-10-09

申请人： Ibiden Co., Ltd.

发明人： SAKAMOTO, Hajime ,  KAWANO, Shuichi ,  KOMATSU, Daiki ,  SEGAWA, Hiroshi

IPC分类号： H01L23/32 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC分类号： H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： The present invention is intended to provide an interposer that can lower mounting height and draw multiple wires with the smallest possible number of layers, and that is suitable for high-volume signal transmissions between electronic components, and the interposer of the present invention comprises:
a first insulating layer composed of an inorganic material;
a first land formed in the first insulating layer;
a second land formed in the first insulating layer;
a first wire formed in the first insulating layer to electrically connect the first land and the second land;
a second insulating layer formed on a first surface of the first insulating layer, the first land, the second land, and the first wire, having a first opening for a first via conductor connected to the second land;
a first pad for loading a first electronic component mounted on a second side of the first insulating layer;
a second pad for loading a second electronic component, formed on the second insulating layer;
a second wire formed on the second insulating layer; and
a first via conductor formed in the first opening to electrically connect the first land and the second wire,
wherein the first pad and the second pad are electrically connected via the first wire and the second wire, and the second wire has a longer wire length and a greater thickness than the first wire.

公开(公告)号：EP1667227A4

公开(公告)日：2011-08-03

申请号：EP05703870

申请日：2005-01-20

申请人： PANASONIC CORP

发明人： NAKATANI SEIICHI ,  MITANI TSUTOMU

IPC分类号： H01L25/18 ,  H01L23/31 ,  H01L23/66 ,  H01L25/04 ,  H01L25/065 ,  H01L25/10 ,  H05K1/02 ,  H05K1/18

CPC分类号： H05K1/02 ,  H01L23/3128 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H05K1/181 ,  H05K2201/10098 ,  H05K2201/1053 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A module that can not only achieve the reduction in size and manufacturing cost but also be impervious to noise due to electromagnetic waves, and a mounted structure using the same are provided. A module (1) includes a substrate (12) and a plurality of semiconductor packages (11a, 11b), each including a semiconductor chip (10), mounted on the substrate (12). Each of the plurality of semiconductor packages (11a, 11b) includes a first radio communication element (16) for transmitting and receiving a signal between the semiconductor chips (10) in the plurality of semiconductor packages (11a, 11b) by radio communication, and the first radio communication element (16) is constituted independently of the semiconductor chip (10).

摘要翻译： 提供了一种不仅可以实现尺寸和制造成本的降低，而且还可以防止由于电磁波而产生的噪声的模块，并且提供了使用其的安装结构。 模块（1）包括基板（12）和多个半导体封装（11a，11b），每个半导体封装包括安装在基板（12）上的半导体芯片（10）。 多个半导体封装（11a，11b）中的每一个包括用于通过无线电通信在多个半导体封装（11a，11b）中的半导体芯片（10）之间发送和接收信号的第一无线电通信元件（16），以及 第一无线电通信元件（16）独立于半导体芯片（10）构成。

公开(公告)号：EP2347440A1

公开(公告)日：2011-07-27

申请号：EP09761006.7

申请日：2009-11-16

申请人： NXP B.V.

发明人： DE GRAAUW, Antonius Johannes Matheus ,  VAN STRATEN, Freek Egbert

IPC分类号： H01L23/66 ,  H01L23/498 ,  H01Q1/38 ,  H01Q23/00

CPC分类号： H01L23/66 ,  H01L23/49816 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/3011 ,  H01Q23/00 ,  H01L2224/0401

摘要： A millimeter-wave radio antenna module (600) comprising: an antenna substrate (603) having an antenna (602) provided on a face thereof; and a semiconductor die (601) comprising a wireless system IC, the die mounted on a face of the antenna substrate and configured to provide a signal to the antenna, wherein a ball grid array (605) is formed on a face of the antenna substrate for mounting the antenna module to a circuit board, the ball grid array being configured to define an air dielectric gap (606) between the antenna and the circuit board.