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公开(公告)号：EP0331911A3
公开(公告)日：1991-06-05
申请号：EP89101995.2
申请日：1989-02-06
IPC分类号： G11C11/24 , H01L27/108
CPC分类号： H01L27/10861 , G11C11/405 , H01L27/108
摘要： A charge amplifying memory cell and its method of making based on trench technology. A trench is formed which reaches through an n-type well region (32) to a p⁺-type substrate (30). A triple layer (36, 38, 40) is formed on two sidewalls of the trench consisting of two capacitive insulating layers and a intermediate p⁺ polysilicon layer. The trench is then at least partially filled with a conductor, such as polysilicon (42), facing the triple layer. Thereby, the intermediate polysilicon layer acts as a charge storage node with capacitance to both the substrate and the polysilicon filling the trench. The insulating layer facing the well is opened with a contact hole near its top so that a p⁺ transistor drain (44) is formed in the adjacent well by diffusion from the polysilicon through the contact hole. A p⁺ transistor source (50) is doped into the well with a gate region between it and the drain to provide a write transistor. A p+ region (46) is also formed adjacent a sidewall of the trench other than the one containing the contact hole so that a read transistor is vertically formed in the n-type well between it and the substrate. The intermediate p⁺ polysilicon layer acts as the electrode of this read transistor, whereby stored charge is amplified by the read transistor.
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公开(公告)号：EP0331911A2
公开(公告)日：1989-09-13
申请号：EP89101995.2
申请日：1989-02-06
IPC分类号： G11C11/24 , H01L27/108
CPC分类号： H01L27/10861 , G11C11/405 , H01L27/108
摘要： A charge amplifying memory cell and its method of making based on trench technology. A trench is formed which reaches through an n-type well region (32) to a p⁺-type substrate (30). A triple layer (36, 38, 40) is formed on two sidewalls of the trench consisting of two capacitive insulating layers and a intermediate p⁺ polysilicon layer. The trench is then at least partially filled with a conductor, such as polysilicon (42), facing the triple layer. Thereby, the intermediate polysilicon layer acts as a charge storage node with capacitance to both the substrate and the polysilicon filling the trench. The insulating layer facing the well is opened with a contact hole near its top so that a p⁺ transistor drain (44) is formed in the adjacent well by diffusion from the polysilicon through the contact hole. A p⁺ transistor source (50) is doped into the well with a gate region between it and the drain to provide a write transistor. A p+ region (46) is also formed adjacent a sidewall of the trench other than the one containing the contact hole so that a read transistor is vertically formed in the n-type well between it and the substrate. The intermediate p⁺ polysilicon layer acts as the electrode of this read transistor, whereby stored charge is amplified by the read transistor.
摘要翻译： 一种电荷放大存储单元及其基于沟槽技术制造的方法。 形成沟槽，其通过n型阱区域（32）到达p +型衬底（30）。 在由两个电容绝缘层和中间p +多晶硅层组成的沟槽的两个侧壁上形成三层（36,38,40）。 然后，沟槽至少部分地填充有面向三层的导体，例如多晶硅（42）。 由此，中间多晶硅层充当具有电荷的电荷存储节点，同时衬底和填充沟槽的多晶硅。 面向井的绝缘层在其顶部附近具有接触孔打开，使得通过从多晶硅通过接触孔的扩散在相邻阱中形成p +晶体管漏极（44）。 将p + +晶体管源极（50）掺杂到阱中并在其与漏极之间的栅极区域以提供写入晶体管。 除了包含接触孔的沟槽的侧壁之外，还形成有p +区域（46），使得读取晶体管垂直形成在其与衬底之间的n型阱中。 中间p +多晶硅层用作该读晶体管的电极，由此存储的电荷由读晶体管放大。
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23.发明公开Dynamic RAM cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes 失效具有三角形定义的桥接触点和门电极的具有共享的TRENCH存储电容器的动态RAM单元
公开(公告)号：EP0264858A3
公开(公告)日：1989-06-28
申请号：EP87115186.6
申请日：1987-10-16
CPC分类号： H01L27/10861 , H01L21/28525 , H01L27/10829 , Y10S257/90
摘要： A one-device shared trench memory cell, in which the polysilicon (22,24) and dielectric layers (26,26A) within the trench (20) extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant ions are diffused from the doped polysilicon within the trench to the conformal polysilicon layer, and from the conformal polysilicon layer to a portion of the substrate disposed thereunder (36). The conformal polysilicon is etched in a solvent that preferentially attacks undoped polysilicon, to provide a bridge contact (30) that is self-aligned to the polysilicon within the trench and to the diffusion region. A plurality of FETs formed on either side of the trench, by use of a sidewall-defined gate electrode (34) to maximize density. The cell produces a "poly-to-poly" and "poly-to-substrate" storage capacitor combination that maximizes charge storage capability.
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公开(公告)号：EP0186745A2
公开(公告)日：1986-07-09
申请号：EP85113178.9
申请日：1985-10-17
IPC分类号： G11C11/404
CPC分类号： G11C11/4074 , G11C11/404
摘要： A memory array is provided which includes a common sense line (SL) to which is connected first and second series of cells, each cell of each series includes a storage capacitor (C), switching means (T) and a bit line (BL) connected to a plate of the storage capacitor (C), with a common word line (WL) connected to the control electrodes of each of the switching means. The switching means, preferably field effect transistors, of each series of cells have progressively higher threshold voltages beginning at the sense line, and the voltage applied to the common word line has a magnitude greater than that of the highest threshold voltage. Data is stored into or read from the storage capacitors by selecting the common word line and the bit line of the desired cell in a sequential manner.
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公开(公告)号：EP0070426B1
公开(公告)日：1985-12-27
申请号：EP82105762.7
申请日：1982-06-29
CPC分类号： H01L21/76202 , H01L23/535 , H01L27/10805 , H01L2924/0002 , H01L2924/00
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公开(公告)号：EP0132536A1
公开(公告)日：1985-02-13
申请号：EP84106064.3
申请日：1984-05-28
IPC分类号： H03K17/04 , H03K19/017 , H01L29/78
CPC分类号： H03K17/04106 , H03K19/01735
摘要： A driver circuit is provided which includes a field effect transistor (T1) having first and second spaced apart semiconductor regions (12, 14) of a given conductivity type and a third semiconductor region (16) of a conductivity type opposite to the given conductivity type interposed between the first and second regions (12,14) and having a given sustaining voltage serially connected with a capacitor (C). The circuit further includes means for applying between the first and second spaced apart regions (12, 14) a given supply voltage (V H ) having a magnitude greater than the magnitude of the sustaining voltage (Vs) and less than the breakdown voltage of a PN junction formed in the transistor (T1) and means including a control voltage (V G ) applied to the gate electrode (10) of the transistor (T1) for initiating current flow between the first and second spaced apart regions (12, 14) when the given supply voltage (V H ) is applied between the first and second spaced apart regions (12, 14).
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公开(公告)号：EP0042084A1
公开(公告)日：1981-12-23
申请号：EP81104003.9
申请日：1981-05-25
CPC分类号： H01L29/7827 , H01L21/76877 , H01L27/10841
摘要： High density V-MOSFET device, particularly single transistor memory cells, are provided by use of a series of simplified self-aligning process steps. Gate electrodes, source/drain regions and source/drain contacts are provided with the aid of an initial mask-less photoresist removal process in which a relatively thick layer of self-leveling photoresist is uniformly removed in order to define portions of a gate electrode within the recess of a V-groove. The gate electrode (22) subsequently acts as a self-aligned mask to define implanted source/drain regions (30, 32) also within the V-groove (18) and to enable second level interconnecting metallurgy contacts (34) to be formed along the sidewalls of the V-groove (18) below the level of the surface of the substrate (10, 14).
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公开(公告)号：EP0265616B1
公开(公告)日：1993-12-15
申请号：EP87111966.5
申请日：1987-08-18
CPC分类号： H01L29/66181 , H01L27/10829 , H01L29/945
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公开(公告)号：EP0572943A1
公开(公告)日：1993-12-08
申请号：EP93108663.1
申请日：1993-05-28
IPC分类号： H01L21/3205 , H01L21/82 , H01L27/108 , H01L21/033
CPC分类号： B82Y10/00 , H01L21/0337 , H01L27/10817 , H01L27/10852 , H01L28/92 , Y10S438/964 , Y10S977/78 , Y10S977/784 , Y10S977/887
摘要： A method is provided to enable the formation of sub-lithographic relief images to increase the surface area of semiconductor structures for use in the capacitors of DRAM cells. The method includes the steps of forming in situ a non-planar region (12) having a relief pattern (14) comprising sub-micron sized elements and the transferring the relief pattern (14) into a masking layer (16) in order to selectively etch a substrate (10) to form relatively deep trenches (20) having a density equal to the relief pattern (14). Polysilicon and porous silicon can be used to form the sub-micron relief pattern.
摘要翻译： 提供了一种能够形成亚光刻浮雕图像以增加在DRAM单元的电容器中使用的半导体结构的表面积的方法。 该方法包括以下步骤：原位形成具有包括亚微米尺寸元件的浮雕图案（14）的非平面区域（12），并将浮雕图案（14）转移到掩模层（16）中以便选择性地 蚀刻衬底（10）以形成具有等于浮雕图案（14）的密度的相对较深的沟槽（20）。 可以使用多晶硅和多孔硅来形成亚微米浮雕图案。
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30.发明公开
公开(公告)号：EP0560069A1
公开(公告)日：1993-09-15
申请号：EP93102046.5
申请日：1993-02-10
发明人： Bergendahl, Albert Stephan , Bertin, Claude Louis , Cronin, John Edward , Kalter, Howard Leo , Kenney, Donald McAlpine , Lam, Chung Hon , Lee, Hsing-San
IPC分类号： H01L27/115 , H01L29/788 , H01L27/108
CPC分类号： H01L29/7882 , H01L27/105 , H01L27/1052 , H01L27/10829 , H01L27/115
摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion (11). The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes (5) and continuous horizontally disposed program (22) and recall (18) gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride (7). The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.
摘要翻译： 公开了一种半导体器件存储器阵列，其形成在包括排列成阵列的多个场效应晶体管DRAM器件的半导体衬底上。 每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM- EEPROM对共享共同的漏极扩散（11）。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极（5）和连续水平布置的程序（22）和调用（18）栅极多晶硅电极。 浮动栅极与程序分离并通过富氮氮化物（7）进行调用。 本发明的阵列提供了高密度的阴影RAM。 还公开了用于制造本发明的装置的方法。
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